On 17.12.2024 3:51 PM, Neil Armstrong wrote:
> The Adreno GPU Management Unit (GMU) can also scale the ddr
> bandwidth along the frequency and power domain level, but for
> now we statically fill the bw_table with values from the
> downstream driver.
>
> Only the first entry is used, which is a disable vote, so we
> currently rely on scaling via the linux interconnect paths.
>
> Let's dynamically generate the bw_table with the vote values
> previously calculated from the OPPs.
>
> Those entries will then be used by the GMU when passing the
> appropriate bandwidth level while voting for a gpu frequency.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
> ---
[...]
> + /*
> + * These are the CX (CNOC) votes - these are used by the GMU
> + * The 'CN0' BCM is used on all targets, and votes are basically
> + * 'off' and 'on' states with first bit to enable the path.
> + */
> +
> + msg->cnoc_cmds_addrs[0] = cmd_db_read_addr("CN0");
> + msg->cnoc_cmds_num = 1;
> +
> + msg->cnoc_cmds_data[0][0] = BCM_TCS_CMD(true, false, 0, 0);
> + msg->cnoc_cmds_data[1][0] = BCM_TCS_CMD(true, true, 0, BIT(0));
> +
> + /* Compute the wait bitmask with each BCM having the commit bit */
> + msg->cnoc_wait_bitmask = 0;
> + for (j = 0; j < msg->cnoc_cmds_num; j++)
> + if (msg->cnoc_cmds_data[0][j] & BCM_TCS_CMD_COMMIT_MASK)
> + msg->cnoc_wait_bitmask |= BIT(j);
Still very much not a fan of this.
I think this would be equally telling:
/* Always flush on/off commands */
msg->cnoc_wait_bitmask = BIT(0);
with or without that:
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
Konrad
