On 12/20/2024 3:18 PM, Konrad Dybcio wrote:
> On 20.12.2024 7:42 AM, Manikanta Mylavarapu wrote:
>>
>>
>> On 12/13/2024 8:36 PM, Konrad Dybcio wrote:
>>> On 13.12.2024 2:49 PM, Manikanta Mylavarapu wrote:
>>>> Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices
>>>> found on IPQ5424 platform. The PCIe0 & PCIe1 are 1-lane Gen3
>>>> host whereas PCIe2 & PCIe3 are 2-lane Gen3 host.
>>>>
>>>> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@xxxxxxxxxxx>
>>>> ---
>
> [...]
>
>>>> tlmm: pinctrl@1000000 {
>>>> compatible = "qcom,ipq5424-tlmm";
>>>> @@ -168,11 +261,11 @@ gcc: clock-controller@1800000 {
>>>> reg = <0 0x01800000 0 0x40000>;
>>>> clocks = <&xo_board>,
>>>> <&sleep_clk>,
>>>> + <&pcie0_phy>,
>>>> + <&pcie1_phy>,
>>>> <0>,
>>>
>>> This leftover zero needs to be removed too, currently the wrong
>>> clocks are used as parents
>>>
>>
>> Hi Konrad,
>>
>> The '<0>' entry is for "USB PCIE wrapper pipe clock source".
>> And, will update the pcie entries as follows
>> <&pcie0_phy GCC_PCIE0_PIPE_CLK>
>> <&pcie1_phy GCC_PCIE1_PIPE_CLK>
>> <&pcie2_phy GCC_PCIE2_PIPE_CLK>
>> <&pcie3_phy GCC_PCIE3_PIPE_CLK>
>>
>> Please correct me if i am wrong.
>
> The order of these is fixed by the first enum in
> drivers/clk/qcom/gcc-ipq5424.c. The <0> entry must be at the end of
> the clocks list for it to do what you want it to.
>
I understand your point. I will move the <0> entry to the end and
incorporate this change in the next version.
Thanks & Regards,
Manikanta.
