On Thu, Dec 19, 2024 at 03:49:20PM +0800, Jun Nie wrote:
> Currently if DSC support is requested, the driver only supports using
> 2 DSC blocks. We need 4 DSC in quad-pipe topology in future. So let's
> only configure DSC engines in use, instead of the maximum number of
> DSC engines.
>
> Signed-off-by: Jun Nie <jun.nie@xxxxxxxxxx>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 650df585138cd..cc23f364dd080 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -2028,6 +2028,7 @@ static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
> struct drm_dsc_config *dsc)
> {
> /* coding only for 2LM, 2enc, 1 dsc config */
Is the comment still relevant?
> + int num_dsc = dpu_enc->num_dscs;
> struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
> struct dpu_hw_ctl *ctl = enc_master->hw_ctl;
> struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
> @@ -2039,7 +2040,7 @@ static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
> u32 initial_lines;
> int i;
>
> - for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
> + for (i = 0; i < num_dsc; i++) {
> hw_pp[i] = dpu_enc->hw_pp[i];
> hw_dsc[i] = dpu_enc->hw_dsc[i];
>
> @@ -2068,7 +2069,7 @@ static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
> enc_ip_w = intf_ip_w / 2;
> initial_lines = dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
>
> - for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
> + for (i = 0; i < num_dsc; i++)
> dpu_encoder_dsc_pipe_cfg(ctl, hw_dsc[i], hw_pp[i],
> dsc, dsc_common_mode, initial_lines);
> }
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
