From: Jie Zhang <quic_jiezh@xxxxxxxxxxx> Add support for Adreno 612 GPU found in SM6150/QCS615 chipsets. A612 falls under ADRENO_6XX_GEN1 family and is a cut down version of A615 GPU. A612 has a new IP called Reduced Graphics Management Unit or RGMU which is a small state machine which helps to toggle GX GDSC (connected to CX rail) to implement IFPC feature. It doesn't support any other features of a full fledged GMU like clock control, resource voting to rpmh etc. So we need linux clock driver support like other gmu-wrapper implementations to control gpu core clock and gpu GX gdsc. Since there is no benefit with enabling RGMU at the moment, RGMU is entirely skipped in this patch. Signed-off-by: Jie Zhang <quic_jiezh@xxxxxxxxxxx> Signed-off-by: Akhil P Oommen <quic_akhilpo@xxxxxxxxxxx> Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx> --- Mesa support is already available for A612. Verified Glmark2 with weston. Some dependencies for the devicetree change are not yet available in the mailing lists. I will send it out as a separate patch later. --- Changes in v3: - Drop the NO_SYSCACHE quirk patch (Konrad/Rob) - Use the new "qcom,adreno-rgmu" compatible string (Konrad) - Link to v2: https://lore.kernel.org/r/20241125-a612-gpu-support-v2-0-b7cc38e60191@xxxxxxxxxxx Changes in v2: - Added a new quirk to check LLC support (new patch). This helps to correct LLC handling in A612's patch. - Rebased on msm-next tip - Captured R-b from Konrad - Link to v1: https://lore.kernel.org/r/20241101-a612-gpu-support-v1-1-bdfe8f6d9306@xxxxxxxxxxx --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 15 ++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 47 ++++++++++++++++++++++--------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 11 ++++++-- 3 files changed, 57 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 0c560e84ad5a..234083b69844 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -704,6 +704,21 @@ static const struct adreno_info a6xx_gpus[] = { { 157, 3 }, { 127, 4 }, ), + }, { + .chip_ids = ADRENO_CHIP_IDS(0x06010200), + .family = ADRENO_6XX_GEN1, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + }, + .gmem = (SZ_128K + SZ_4K), + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + .a6xx = &(const struct a6xx_info) { + .hwcg = a612_hwcg, + .protect = &a630_protect, + .gmu_cgc_mode = 0x00000022, + .prim_fifo_threshold = 0x00080000, + }, }, { .chip_ids = ADRENO_CHIP_IDS(0x06010500), .family = ADRENO_6XX_GEN1, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 019610341df1..630932693951 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -504,15 +504,26 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) if (adreno_is_a630(adreno_gpu)) clock_cntl_on = 0x8aa8aa02; - else if (adreno_is_a610(adreno_gpu)) + else if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu)) clock_cntl_on = 0xaaa8aa82; else if (adreno_is_a702(adreno_gpu)) clock_cntl_on = 0xaaaaaa82; else clock_cntl_on = 0x8aa8aa82; - cgc_delay = adreno_is_a615_family(adreno_gpu) ? 0x111 : 0x10111; - cgc_hyst = adreno_is_a615_family(adreno_gpu) ? 0x555 : 0x5555; + if (adreno_is_a612(adreno_gpu)) + cgc_delay = 0x11; + else if (adreno_is_a615_family(adreno_gpu)) + cgc_delay = 0x111; + else + cgc_delay = 0x10111; + + if (adreno_is_a612(adreno_gpu)) + cgc_hyst = 0x55; + else if (adreno_is_a615_family(adreno_gpu)) + cgc_delay = 0x555; + else + cgc_delay = 0x5555; gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); @@ -600,6 +611,9 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) gpu->ubwc_config.ubwc_swizzle = 0x7; } + if (adreno_is_a612(gpu)) + gpu->ubwc_config.highest_bank_bit = 13; + if (adreno_is_a618(gpu)) gpu->ubwc_config.highest_bank_bit = 14; @@ -1165,7 +1179,7 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); /* Setting the mem pool size */ - if (adreno_is_a610(adreno_gpu)) { + if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu)) { gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48); gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47); } else if (adreno_is_a702(adreno_gpu)) { @@ -1199,7 +1213,7 @@ static int hw_init(struct msm_gpu *gpu) /* Enable fault detection */ if (adreno_is_a730(adreno_gpu) || - adreno_is_a740_family(adreno_gpu)) + adreno_is_a740_family(adreno_gpu) || adreno_is_a612(adreno_gpu)) gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0xcfffff); else if (adreno_is_a690(adreno_gpu)) gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x4fffff); @@ -1863,8 +1877,8 @@ static void a7xx_llc_activate(struct a6xx_gpu *a6xx_gpu) static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu) { - /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ - if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) + /* A612 is actually not a gmu-wrapper and has LLCC */ + if (adreno_has_gmu_wrapper(&a6xx_gpu->base) && !adreno_is_a612(&a6xx_gpu->base)) return; llcc_slice_putd(a6xx_gpu->llc_slice); @@ -1876,8 +1890,8 @@ static void a6xx_llc_slices_init(struct platform_device *pdev, { struct device_node *phandle; - /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ - if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) + /* A612 is actually not a gmu-wrapper and has LLCC */ + if (adreno_has_gmu_wrapper(&a6xx_gpu->base) && !adreno_is_a612(&a6xx_gpu->base)) return; /* @@ -2081,6 +2095,9 @@ static int a6xx_pm_resume(struct msm_gpu *gpu) if (!ret) msm_devfreq_resume(gpu); + if (adreno_is_a612(&a6xx_gpu->base)) + a6xx_llc_activate(a6xx_gpu); + return ret; } @@ -2120,6 +2137,9 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu) trace_msm_gpu_suspend(0); + if (adreno_is_a612(&a6xx_gpu->base)) + a6xx_llc_deactivate(a6xx_gpu); + msm_devfreq_suspend(gpu); mutex_lock(&a6xx_gpu->gmu.lock); @@ -2475,7 +2495,9 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) /* FIXME: How do we gracefully handle this? */ BUG_ON(!node); - adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper"); + /* We do not support RGMU at the moment, so assume it is a gmu wrapper for now */ + adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper") || + of_device_is_compatible(node, "qcom,adreno-rgmu"); adreno_gpu->base.hw_apriv = !!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); @@ -2485,11 +2507,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) config->info->family == ADRENO_7XX_GEN2 || config->info->family == ADRENO_7XX_GEN3; - a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); - ret = a6xx_set_supported_hw(&pdev->dev, config->info); if (ret) { - a6xx_llc_slices_destroy(a6xx_gpu); kfree(a6xx_gpu); return ERR_PTR(ret); } @@ -2508,6 +2527,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) return ERR_PTR(ret); } + a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); + /* * For now only clamp to idle freq for devices where this is known not * to cause power supply issues: diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index e71f420f8b3a..61b9141a63ab 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -420,6 +420,11 @@ static inline int adreno_is_a610(const struct adreno_gpu *gpu) return adreno_is_revn(gpu, 610); } +static inline int adreno_is_a612(const struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] == 0x06010200; +} + static inline int adreno_is_a618(const struct adreno_gpu *gpu) { return adreno_is_revn(gpu, 618); @@ -489,9 +494,9 @@ static inline int adreno_is_a610_family(const struct adreno_gpu *gpu) { if (WARN_ON_ONCE(!gpu->info)) return false; - - /* TODO: A612 */ - return adreno_is_a610(gpu) || adreno_is_a702(gpu); + return adreno_is_a610(gpu) || + adreno_is_a612(gpu) || + adreno_is_a702(gpu); } /* TODO: 615/616 */ --- base-commit: f4a867a46862c1743501bbe8c813238456ec8699 change-id: 20241031-a612-gpu-support-d6330f17d01f Best regards, -- Akhil P Oommen <quic_akhilpo@xxxxxxxxxxx>
