On 06/12/2024 07:51, Sahil Chandna wrote:
> The industrial mezzanine kit enhances the capabilities of QCS6490
> rb3gen2 core kit. Add support for industrial mezzanine board.
>
> Signed-off-by: Sahil Chandna <quic_chandna@xxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 3 ++
> .../qcs6490-rb3gen2-industrial-mezzanine.dtso | 44 +++++++++++++++++++
> 2 files changed, 47 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 6ca8db4b8afe..6fe5a5ccd950 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -111,6 +111,9 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb
> +
> +qcs6490-rb3gen2-industrial-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-industrial-mezzanine.dtbo
I don't see your finial overlay being applied.
> +
> dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb
> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
> new file mode 100644
> index 000000000000..74f2f782d166
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
> @@ -0,0 +1,44 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +/*
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include "pm7250b.dtsi"
> +#include "sc7280.dtsi"
> +
> +&pm7250b_gpios {
> + gpio5_tpm_dig_out {
It does not look like you tested the DTS against bindings. Please run
`make dtbs_check W=1` (see
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).
> + gpio5_dig_out_default: gpio5_dig_out_default {
Please follow DTS coding style.
> + pins = "gpio5";
> + function = "normal";
> + power-source = <1>;
> + output-high;
> + input-disable;
> + bias-pull-up;
> + qcom,drive-strength = <3>;
> + };
> + };
> +};
> +
> +&qupv3_id_1 {
> + status = "okay";
> +};
> +
> +&spi11 {
> + status = "okay";
> +
> + st33htpm0: st33htpm@0 {
Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> + compatible = "st,st33htpm-spi";
> + reg = <0>;
> + spi-max-frequency = <20000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&gpio5_dig_out_default>;
> + status="okay";
Drop
> + };
> +};
> --
> 2.17.1
Best regards,
Krzysztof
