On Mon, May 09, 2016 at 06:14:30PM +0530, Abhishek Sahu wrote: > 1. Current QCOM I2C driver hangs when sending data to address 0x03-0x07 > in some scenarios. The QUP controller generates invalid write in this > case, since these addresses are reserved for different bus formats. > > 2. Also, the error handling is done by I2C QUP ISR in the case of DMA > mode. The state need to be RESET in case of any error for clearing the > available data in FIFO, which otherwise leaves the BAM DMA controller > in hang state. > > This patch fixes the above two issues by clearing the error bits from > I2C and QUP status in ISR in case of I2C error, QUP error and resets > the QUP state to clear the FIFO data. > > Signed-off-by: Abhishek Sahu <absahu@xxxxxxxxxxxxxx> Applied to for-next, thanks!
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