Adds data and clock pins description (their active state) of
soundwire masters and onboard DMIC.
Cc: Srinivas Kandagatla <srinivas.kandagatla@xxxxxxxxxx>
Signed-off-by: Alexey Klimov <alexey.klimov@xxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sm4250.dtsi | 62 ++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm4250.dtsi b/arch/arm64/boot/dts/qcom/sm4250.dtsi
index cd8c8e59976e..723391ba9aa2 100644
--- a/arch/arm64/boot/dts/qcom/sm4250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm4250.dtsi
@@ -37,10 +37,36 @@ &cpu7 {
compatible = "qcom,kryo240";
};
+&swr0 {
+ pinctrl-0 = <&lpass_tx_swr_active>;
+ pinctrl-names = "default";
+};
+
+&swr1 {
+ pinctrl-0 = <&lpass_rx_swr_active>;
+ pinctrl-names = "default";
+};
+
&lpass_tlmm {
compatible = "qcom,sm4250-lpass-lpi-pinctrl";
gpio-ranges = <&lpass_tlmm 0 0 27>;
+ lpass_dmic01_active: lpass-dmic01-active-state {
+ clk-pins {
+ pins = "gpio6";
+ function = "dmic01_clk";
+ drive-strength = <8>;
+ output-high;
+ };
+
+ data-pins {
+ pins = "gpio7";
+ function = "dmic01_data";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
lpi_i2s2_active: lpi-i2s2-active-state {
sck-pins {
pins = "gpio10";
@@ -74,4 +100,40 @@ ext-mclk1-pins {
output-high;
};
};
+
+ lpass_tx_swr_active: lpass-tx-swr-active-state {
+ clk-pins {
+ pins = "gpio0";
+ function = "swr_tx_clk";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio1", "gpio2";
+ function = "swr_tx_data";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-bus-hold;
+ };
+ };
+
+ lpass_rx_swr_active: lpass-rx-swr-active-state {
+ clk-pins {
+ pins = "gpio3";
+ function = "swr_rx_clk";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio4", "gpio5";
+ function = "swr_rx_data";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-bus-hold;
+ };
+ };
};
--
2.45.2
