This series adds document, phy, configs support for PCIe in QCS8300. The series depend on the following devicetree. Base DT: https://lore.kernel.org/all/20240925-qcs8300_initial_dtsi-v2-0-494c40fa2a42@xxxxxxxxxxx/ Signed-off-by: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@xxxxxxxxxxx> --- Have follwing changes: - Document the QMP PCIe PHY on the QCS8300 platform. - Add dedicated schema for the PCIe controllers found on QCS8300. - Add compatible for qcs8300 platform. - Add configurations in devicetree for PCIe0, including registers, clocks, interrupts and phy setting sequence. - Add configurations in devicetree for PCIe1, including registers, clocks, interrupts and phy setting sequence. Changes in v2: - Fix some format comments - Add global interrupt for PCIe0 and PCIe1 - split the soc dtsi and the platform dts into two changes - Link to v1: https://lore.kernel.org/all/20241114095409.2682558-1-quic_ziyuzhan@xxxxxxxxxxx/ Ziyue Zhang (8): dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS8300 QMP PCIe PHY Gen4 x2 phy: qcom-qmp-pcie: add dual lane PHY support for QCS8300 dt-bindings: PCI: qcom,pcie-sa8775p: document qcs8300 PCI: qcom: Add QCS8300 PCIe support arm64: dts: qcom: qcs8300: enable pcie0 for qcs8300 platform arm64: dts: qcom: qcs8300: enable pcie0 for qcs8300 soc arm64: dts: qcom: qcs8300: enable pcie1 for qcs8300 soc arm64: dts: qcom: qcs8300: enable pcie1 for qcs8300 platform .../bindings/pci/qcom,pcie-sa8775p.yaml | 7 +- .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 + arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 86 ++++- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 352 ++++++++++++++++++ drivers/pci/controller/dwc/pcie-qcom.c | 1 + drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 89 +++++ 6 files changed, 534 insertions(+), 3 deletions(-) base-commit: eb6a0b56032c62351a59a12915a89428bce68d1d -- 2.34.1
