On Tue, Nov 26, 2024 at 05:35:05PM +0800, Tingguo Cheng wrote:
> Add the SPMI bus arbiter node for QCS8300 SoC which connected
> with PMICs on QCS8300 boards.
Could you please comment, what is the version of the SPMI controller /
arbiter?
>
> Signed-off-by: Tingguo Cheng <quic_tingguoc@xxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> index 2c35f96c3f289d5e2e57e0e30ef5e17cd1286188..03bf72d6ec5c9ec92f6f53df9253c8c5953e13c4 100644
> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> @@ -939,6 +939,28 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
> #clock-cells = <0>;
> };
>
> + spmi_bus: spmi@c440000 {
> + compatible = "qcom,spmi-pmic-arb";
> + reg = <0x0 0x0c440000 0x0 0x1100>,
> + <0x0 0x0c600000 0x0 0x2000000>,
> + <0x0 0x0e600000 0x0 0x100000>,
> + <0x0 0x0e700000 0x0 0xa0000>,
> + <0x0 0x0c40a000 0x0 0x26000>;
> + reg-names = "core",
> + "chnls",
> + "obsrvr",
> + "intr",
> + "cnfg";
> + qcom,channel = <0>;
> + qcom,ee = <0>;
> + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "periph_irq";
> + interrupt-controller;
> + #interrupt-cells = <4>;
> + #address-cells = <2>;
> + #size-cells = <0>;
> + };
> +
> tlmm: pinctrl@f100000 {
> compatible = "qcom,qcs8300-tlmm";
> reg = <0x0 0x0f100000 0x0 0x300000>;
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
