On 11/26/2024 12:12 AM, Dmitry Baryshkov wrote:
On Mon, Nov 25, 2024 at 11:04:49AM +0530, Renjiang Han wrote:
Add support for Qualcomm video acceleration hardware used for video
stream decoding and encoding on QCOM QCS615.
Signed-off-by: Renjiang Han <quic_renjiang@xxxxxxxxxxx>
---
.../bindings/media/qcom,qcs615-venus.yaml | 182 +++++++++++++++++++++
1 file changed, 182 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/qcom,qcs615-venus.yaml b/Documentation/devicetree/bindings/media/qcom,qcs615-venus.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..7a3a01ff06d8b62bc2424a0a24857c86c6865f89
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,qcs615-venus.yaml
@@ -0,0 +1,182 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,qcs615-venus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QCS615 Venus video encode and decode accelerators
+
+maintainers:
+ - Stanimir Varbanov <stanimir.k.varbanov@xxxxxxxxx>
+ - Vikash Garodia <quic_vgarodia@xxxxxxxxxxx>
+
+description:
+ The Venus IP is a video encode and decode accelerator present
+ on Qualcomm platforms
+
+allOf:
+ - $ref: qcom,venus-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,qcs615-venus
Please extend sc7180-venus.yaml instead. No need to duplicate
unnecessary things.
Thanks for your review. But I'm sorry I can't get it. The devicetree for
qcs615-venus is in qcs615.dtsi. I'm not sure how to use sc7180-venus.yaml
instead.
+
+ power-domains:
+ minItems: 2
+ maxItems: 3
So, is it 2 or 3? You don't have legacy here, so you should know an
exact number.
Got it. Both minItems and maxItems should be 3. I'll update with next
version.
+
+ power-domain-names:
+ minItems: 2
And this one also can go away.
OK. Thanks for pointing it out. I'll remove this minItems with next
version.
+ items:
+ - const: venus
+ - const: vcodec0
+ - const: cx
+
+ clocks:
+ maxItems: 5
+
+ clock-names:
+ items:
+ - const: core
+ - const: iface
+ - const: bus
+ - const: vcodec0_core
+ - const: vcodec0_bus
+
+ iommus:
+ maxItems: 1
+
+ memory-region:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: video-mem
+ - const: cpu-cfg
+
+ operating-points-v2: true
+
+ opp-table:
+ type: object
+
+ video-decoder:
+ type: object
+
+ additionalProperties: false
+
+ properties:
+ compatible:
+ const: venus-decoder
+
+ required:
+ - compatible
+
+ video-encoder:
+ type: object
+
+ additionalProperties: false
+
+ properties:
+ compatible:
+ const: venus-encoder
+
+ required:
+ - compatible
+
+required:
+ - compatible
+ - power-domain-names
+ - iommus
+ - video-decoder
+ - video-encoder
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,qcs615-videocc.h>
+ #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ venus: video-codec@aa00000 {
+ compatible = "qcom,qcs615-venus";
+ reg = <0xaa00000 0x100000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
+ <&videocc VIDEO_CC_VENUS_AHB_CLK>,
+ <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
+ <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
+ <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
+ clock-names = "core",
+ "iface",
+ "bus",
+ "vcodec0_core",
+ "vcodec0_bus";
+
+ power-domains = <&videocc VENUS_GDSC>,
+ <&videocc VCODEC0_GDSC>,
+ <&rpmhpd RPMHPD_CX>;
+ power-domain-names = "venus",
+ "vcodec0",
+ "cx";
+
+ operating-points-v2 = <&venus_opp_table>;
+
+ interconnects = <&mmss_noc MASTER_VIDEO_P0 0
+ &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0
+ &config_noc SLAVE_VENUS_CFG 0>;
+ interconnect-names = "video-mem",
+ "cpu-cfg";
+
+ iommus = <&apps_smmu 0xe40 0x20>;
+
+ memory-region = <&pil_video_mem>;
+
+ video-decoder {
+ compatible = "venus-decoder";
+ };
+
+ video-encoder {
+ compatible = "venus-encoder";
+ };
+
+ venus_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-133330000 {
+ opp-hz = /bits/ 64 <133330000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-240000000 {
+ opp-hz = /bits/ 64 <240000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-380000000 {
+ opp-hz = /bits/ 64 <380000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-410000000 {
+ opp-hz = /bits/ 64 <410000000>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ };
+
+ opp-460000000 {
+ opp-hz = /bits/ 64 <460000000>;
+ required-opps = <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+ };
--
2.34.1
--
Best Regards,
Renjiang
