Current way of programming of the UBWC-related registers has been
inherited from vendor's drivers. The ubwc_static was supposed to contain
raw data to be programmed to the hardware, but was later repurposed to
define of the bits. As it can be seen by the commit 3e30296b374a
("drm/msm: fix the highest_bank_bit for sc7180") sometimes this data
gets out of sync.
Rework existing msm_mdss_setup_ubwc_dec_NN() functions to be closer to
the actual hardware bit definitions. Drop the ubwc_static field.
Unfortunately this also introduces several "unknown" bits, for which we
do not document the actual purpose. Hopefully comparing this data with
the more documented Adreno UBWC feature bits will provide information
about the meaning of those bits.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
Changes in v2:
- Dropped applied patches
- Added defines for UBWC_AMSBC, UBWC_MIN_ACC_LEN and UBWC_BANK_SPREAD
and .ubwc_bank_spread flag in struct msm_mdss_data (kudos to Abhinav
for helping to handle this on Qualcomm side)
- Changed msm_mdss_data to use true/false to set macrotile_mode
- Link to v1: https://lore.kernel.org/r/20240921-msm-mdss-ubwc-v1-0-411dcf309d05@xxxxxxxxxx
---
Dmitry Baryshkov (3):
drm/msm/mdss: define bitfields for the UBWC_STATIC register
drm/msm/mdss: reuse defined bitfields for UBWC 2.0
drm/msm/mdss: use boolean values for macrotile_mode
drivers/gpu/drm/msm/msm_mdss.c | 71 ++++++++++++++++----------
drivers/gpu/drm/msm/msm_mdss.h | 4 +-
drivers/gpu/drm/msm/registers/display/mdss.xml | 11 +++-
3 files changed, 55 insertions(+), 31 deletions(-)
---
base-commit: 86313a9cd152330c634b25d826a281c6a002eb77
change-id: 20240921-msm-mdss-ubwc-105589e05f35
Best regards,
--
Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
