From: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
The Surface Laptops have a Realtek RTS5261 SD Card reader connected
over a Gen1x1 link to the PCIe3 host. Set up the necessary bits to
make it functional.
Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
---
.../boot/dts/qcom/x1e80100-microsoft-romulus.dtsi | 63 ++++++++++++++++++++++
1 file changed, 63 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi
index 6aea8f3573e834273d56448da772edd27855efec..66a12b20b096baa7d5cf8c5fb65927b765aa18ff 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi
@@ -767,6 +767,27 @@ &mdss_dp3_phy {
status = "okay";
};
+&pcie3 {
+ perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>;
+
+ /* The power supply enable GPIOs are reserved by the secure firmware */
+
+ pinctrl-0 = <&pcie3_default>;
+ pinctrl-names = "default";
+
+ /* The RTS5261 chip on the other side only does Gen1x1 anyway */
+ max-link-speed = <1>;
+ status = "okay";
+};
+
+&pcie3_phy {
+ vdda-phy-supply = <&vreg_l3c>;
+ vdda-pll-supply = <&vreg_l3e>;
+
+ status = "okay";
+};
+
&pcie4 {
status = "okay";
};
@@ -797,6 +818,25 @@ &pcie6a_phy {
status = "okay";
};
+&pm8550ve_2_gpios {
+ sde7_main_reg_en: sde7-main-reg-en-state {
+ pins = "gpio6";
+ function = "normal";
+ };
+
+ sde7_aux_reg_en: sde7-aux-reg-en-state {
+ pins = "gpio8";
+ function = "normal";
+ };
+};
+
+&pm8550ve_8_gpios {
+ vreg_12v_x8_en: 12v-x8-reg-en-state {
+ pins = "gpio8";
+ function = "normal";
+ };
+};
+
&pmc8380_3_gpios {
edp_bl_en: edp-bl-en-state {
pins = "gpio4";
@@ -946,6 +986,29 @@ ssam_state: ssam-state-state {
bias-disable;
};
+ pcie3_default: pcie3-default-state {
+ perst-n-pins {
+ pins = "gpio143";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ clkreq-n-pins {
+ pins = "gpio144";
+ function = "pcie3_clk";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake-n-pins {
+ pins = "gpio145";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
pcie6a_default: pcie6a-default-state {
perst-n-pins {
pins = "gpio152";
--
2.47.0
