On 12.11.2024 1:49 AM, Melody Olvera wrote:
> Add the base dtsi for the SM8750 SoC describing the CPUs, GCC and
> RPMHCC clock controllers, geni UART, interrupt controller, TLMM,
> reserved memory, interconnects, and SMMU.
>
> Co-developed-by: Taniya Das <quic_tdas@xxxxxxxxxxx>
> Signed-off-by: Taniya Das <quic_tdas@xxxxxxxxxxx>
> Co-developed-by: Jishnu Prakash <quic_jprakash@xxxxxxxxxxx>
> Signed-off-by: Jishnu Prakash <quic_jprakash@xxxxxxxxxxx>
> Co-developed-by: Raviteja Laggyshetty <quic_rlaggysh@xxxxxxxxxxx>
> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@xxxxxxxxxxx>
> Signed-off-by: Melody Olvera <quic_molvera@xxxxxxxxxxx>
> ---
[...]
> + power-domain-names = "psci";
> + cpu-idle-states = <&cluster0_c4>;
So here and on x1 we use cpu-idle-states instead of putting the idle state
under domain-idle-states in CPU_PDn like on other PSCI OSI mode-supporting
SoCs. IIUC it works out to be the same thing, but maybe we should stick
to the latter for consistency
[...]
> +
> + gic_its: msi-controller@16040000 {
> + compatible = "arm,gic-v3-its";
> + reg = <0x0 0x16040000 0x0 0x20000>;
> +
> + msi-controller;
> + #msi-cells = <1>;
> +
> + status = "disabled";
> + };
Any reason it's disabled?
LGTM otherwise
Konrad
