On Wed, Nov 13, 2024 at 04:48:28PM +0100, Neil Armstrong wrote:
> The Adreno GMU Management Unit (GNU) can also scale the DDR Bandwidth
> along the Frequency and Power Domain level, but by default we leave the
> OPP core vote for the interconnect ddr path.
>
> While scaling via the interconnect path was sufficient, newer GPUs
> like the A750 requires specific vote paremeters and bandwidth to
> achieve full functionality.
>
> Add a new Quirk enabling DDR Bandwidth vote via GMU.
Please describe, why this is defined as a quirk rather than a proper
platform-level property. From my experience with 6xx and 7xx, all the
platforms need to send some kind of BW data to the GMU.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
> ---
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index e71f420f8b3a8e6cfc52dd1c4d5a63ef3704a07f..20b6b7f49473d42751cd4fb4fc82849be42cb807 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -57,6 +57,7 @@ enum adreno_family {
> #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3)
> #define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4)
> #define ADRENO_QUIRK_PREEMPTION BIT(5)
> +#define ADRENO_QUIRK_GMU_BW_VOTE BIT(6)
>
> /* Helper for formating the chip_id in the way that userspace tools like
> * crashdec expect.
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
