On Thu, Nov 14, 2024 at 02:02:48PM +0100, Konrad Dybcio wrote:
[...]
> > +
> > + pcieport0: pcie@0 {
> > + device_type = "pci";
> > + reg = <0x0 0x0 0x0 0x0 0x0>;
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + ranges;
> > + bus-range = <0x01 0xff>;
> > + };
>
> Are you going to use this? If not, please drop
>
Absolutely not! This describes the IP that is present in the SoC and that IP is
being used. You can however keep it disabled in the soc.dtsi and enable in board
dts when PCIe controller is enabled.
Moreover, I plan to move the slot supplies to this node soon, so it will be
used mostly.
- Mani
--
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