Add venus node into devicetree for the qcs615 video.
Signed-off-by: Renjiang Han <quic_renjiang@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/qcs615.dtsi | 86 ++++++++++++++++++++++++++++++++++++
1 file changed, 86 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index 06deb5c499fe83f0eb20d7957ca14948de7aab34..18ad4da5ed194458aded424560f45a3a9f3163dc 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -394,6 +394,11 @@ smem_region: smem@86000000 {
no-map;
hwlocks = <&tcsr_mutex 3>;
};
+
+ pil_video_mem: pil-video@93400000 {
+ reg = <0x0 0x93400000 0x0 0x500000>;
+ no-map;
+ };
};
soc: soc@0 {
@@ -530,6 +535,87 @@ gem_noc: interconnect@9680000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ venus: video-codec@aa00000 {
+ compatible = "qcom,qcs615-venus";
+ reg = <0x0 0xaa00000 0x0 0x100000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
+ <&videocc VIDEO_CC_VENUS_AHB_CLK>,
+ <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
+ <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
+ <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
+ clock-names = "core",
+ "iface",
+ "bus",
+ "vcodec0_core",
+ "vcodec0_bus";
+
+ power-domains = <&videocc VENUS_GDSC>,
+ <&videocc VCODEC0_GDSC>,
+ <&rpmhpd RPMHPD_CX>;
+ power-domain-names = "venus",
+ "vcodec0",
+ "cx";
+
+ operating-points-v2 = <&venus_opp_table>;
+
+ interconnects = <&mmss_noc MASTER_VIDEO_P0 0
+ &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0
+ &config_noc SLAVE_VENUS_CFG 0>;
+ interconnect-names = "video-mem",
+ "cpu-cfg";
+
+ iommus = <&apps_smmu 0xe40 0x20>;
+
+ memory-region = <&pil_video_mem>;
+
+ status = "disabled";
+
+ video-decoder {
+ compatible = "venus-decoder";
+ };
+
+ video-encoder {
+ compatible = "venus-encoder";
+ };
+
+ venus_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-133330000 {
+ opp-hz = /bits/ 64 <133330000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-240000000 {
+ opp-hz = /bits/ 64 <240000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-380000000 {
+ opp-hz = /bits/ 64 <380000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-410000000 {
+ opp-hz = /bits/ 64 <410000000>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ };
+
+ opp-460000000 {
+ opp-hz = /bits/ 64 <460000000>;
+ required-opps = <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+ };
+
videocc: clock-controller@ab00000 {
compatible = "qcom,qcs615-videocc";
reg = <0 0xab00000 0 0x10000>;
--
2.34.1
