On Sun, Nov 10, 2024 at 9:31 AM Bjorn Andersson
<bjorn.andersson@xxxxxxxxxxxxxxxx> wrote:
>
> Support for per-process page tables requires the SMMU aparture to be
> setup such that the GPU can make updates with the SMMU. On some targets
> this is done statically in firmware, on others it's expected to be
> requested in runtime by the driver, through a SCM call.
>
> One place where configuration is expected to be done dynamically is the
> QCS6490 rb3gen2.
>
> The downstream driver does this unconditioanlly on any A6xx and newer,
nit, s/unconditioanlly/unconditionally/
> so follow suite and make the call.
>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxxxxxxxx>
Reviewed-by: Rob Clark <robdclark@xxxxxxxxx>
> ---
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index 076be0473eb5..75f5367e73ca 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -572,8 +572,19 @@ struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
>
> int adreno_hw_init(struct msm_gpu *gpu)
> {
> + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> + int ret;
> +
> VERB("%s", gpu->name);
>
> + if (adreno_gpu->info->family >= ADRENO_6XX_GEN1 &&
> + qcom_scm_set_gpu_smmu_aperture_is_available()) {
> + /* We currently always use context bank 0, so hard code this */
> + ret = qcom_scm_set_gpu_smmu_aperture(0);
> + if (ret)
> + DRM_DEV_ERROR(gpu->dev->dev, "unable to set SMMU aperture: %d\n", ret);
> + }
> +
> for (int i = 0; i < gpu->nr_rings; i++) {
> struct msm_ringbuffer *ring = gpu->rb[i];
>
>
> --
> 2.45.2
>
