On Fri, Nov 08, 2024 at 11:54:05AM +0530, Taniya Das wrote:
> Add cpufreq-hw node to support cpu frequency scaling.
CPU, not cpu.
Also the prefix is incorrect for both patches.
>
> Signed-off-by: Taniya Das <quic_tdas@xxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 +++++++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index 8c98ac77dc5c665ef296e65ac76c1b59be485abb..2c61da790e78b131e454991c968ece40dd5ca56d 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -33,6 +33,8 @@ cpu0: cpu@0 {
> power-domains = <&cpu_pd0>;
> power-domain-names = "psci";
> next-level-cache = <&l2_0>;
> + clocks = <&cpufreq_hw 0>;
> + qcom,freq-domain = <&cpufreq_hw 0>;
> #cooling-cells = <2>;
>
> l2_0: l2-cache {
> @@ -51,6 +53,8 @@ cpu1: cpu@100 {
> power-domains = <&cpu_pd1>;
> power-domain-names = "psci";
> next-level-cache = <&l2_100>;
> + clocks = <&cpufreq_hw 0>;
> + qcom,freq-domain = <&cpufreq_hw 0>;
>
> l2_100: l2-cache {
> compatible = "cache";
> @@ -68,6 +72,8 @@ cpu2: cpu@200 {
> power-domains = <&cpu_pd2>;
> power-domain-names = "psci";
> next-level-cache = <&l2_200>;
> + clocks = <&cpufreq_hw 0>;
> + qcom,freq-domain = <&cpufreq_hw 0>;
>
> l2_200: l2-cache {
> compatible = "cache";
> @@ -85,6 +91,8 @@ cpu3: cpu@300 {
> power-domains = <&cpu_pd3>;
> power-domain-names = "psci";
> next-level-cache = <&l2_300>;
> + clocks = <&cpufreq_hw 0>;
> + qcom,freq-domain = <&cpufreq_hw 0>;
>
> l2_300: l2-cache {
> compatible = "cache";
> @@ -102,6 +110,8 @@ cpu4: cpu@400 {
> power-domains = <&cpu_pd4>;
> power-domain-names = "psci";
> next-level-cache = <&l2_400>;
> + clocks = <&cpufreq_hw 0>;
> + qcom,freq-domain = <&cpufreq_hw 0>;
>
> l2_400: l2-cache {
> compatible = "cache";
> @@ -119,6 +129,8 @@ cpu5: cpu@500 {
> power-domains = <&cpu_pd5>;
> power-domain-names = "psci";
> next-level-cache = <&l2_500>;
> + clocks = <&cpufreq_hw 0>;
> + qcom,freq-domain = <&cpufreq_hw 0>;
>
> l2_500: l2-cache {
> compatible = "cache";
> @@ -136,6 +148,8 @@ cpu6: cpu@600 {
> power-domains = <&cpu_pd6>;
> power-domain-names = "psci";
> next-level-cache = <&l2_600>;
> + clocks = <&cpufreq_hw 1>;
> + qcom,freq-domain = <&cpufreq_hw 1>;
> #cooling-cells = <2>;
>
> l2_600: l2-cache {
> @@ -154,6 +168,8 @@ cpu7: cpu@700 {
> power-domains = <&cpu_pd7>;
> power-domain-names = "psci";
> next-level-cache = <&l2_700>;
> + clocks = <&cpufreq_hw 1>;
> + qcom,freq-domain = <&cpufreq_hw 1>;
>
> l2_700: l2-cache {
> compatible = "cache";
> @@ -729,6 +745,19 @@ rpmhpd_opp_turbo_l1: opp-9 {
> };
> };
>
> + cpufreq_hw: cpufreq@18323000 {
> + compatible = "qcom,cpufreq-hw";
This doesn't follow the bindings, does it?
> + reg = <0 0x18323000 0 0x1400>,
> + <0 0x18325800 0 0x1400>;
> + reg-names = "freq-domain0", "freq-domain1";
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
> + clock-names = "xo", "alternate";
Are the DCVSH interrupts?
> +
> + #freq-domain-cells = <1>;
> + #clock-cells = <1>;
> + };
> +
> arch_timer: timer {
> compatible = "arm,armv8-timer";
> interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>
> --
> 2.45.2
>
--
With best wishes
Dmitry
