Re: [PATCH] RFC: arm64: dts: qcom: Disable USB U1/U2 entry for QC targets

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On 11/7/2024 4:33 PM, Dmitry Baryshkov wrote:
On Thu, Nov 07, 2024 at 01:06:50PM +0530, Krishna Kurapati wrote:
Enabling U1 and U2 power-saving states can lead to stability and
performance issues, particularly for latency-sensitive or high-
throughput applications. These low-power link states are intended
to reduce power consumption by allowing the device to enter partial
low-power modes during idle periods. However, they can sometimes
result in unexpected behavior. Over the years, some of the issues
seen are as follows:

1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent low power states. These packet drops are often reflected
as Missed Isochronous transfers as the controller was not able to
send the packet in that microframe interval and hence glitches are
seen on the final transmitted video output.

2. On QCS6490-Rb3Gen2 Vision kit, ADB connection is heavily unstable
when U1/U2 is enabled. Often when link enters U2, there is a re-
enumeration seen and device is unusable for many use cases.

3. On QCS8300/QCS9100, it is observed that when Link enters U2, when
the cable is disconnected and reconnected to host PC in HS, there
is no link status change interrupt seen and the plug-in in HS doesn't
show up a bus reset and enumeration failure happens.

4. On older targets like SM8150/SM8250/SM8350, there have been
throughput issues seen during tethering use cases.

To avoid such issues, the USB team at Qualcomm added these quirks
to all targets in the past 4-5 years and extensive testing was done.
Although these are intermittent power states, disabling them didn't
cause any major increase in power numbers.

Signed-off-by: Krishna Kurapati <quic_kriskura@xxxxxxxxxxx>
---
If this is fine, the patch would be made into a series, disabling
U1/U2 for all mobile and QCS targets.

  arch/arm64/boot/dts/qcom/sm8150.dtsi | 4 ++++
  arch/arm64/boot/dts/qcom/sm8250.dtsi | 4 ++++
  arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++++
  arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 ++

Should the same set of quirks be applied to SAR2130P too?

Yes, these two quirks have been added to and tested on SAR2130 downstream. I see that you have added them in your upstream DTSI file too. Thanks for that.

Regards,
Krishna,




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