Adds data and clock pins description (their active state)
of soundwire masters.
Cc: Srinivas Kandagatla <srinivas.kandagatla@xxxxxxxxxx>
Signed-off-by: Alexey Klimov <alexey.klimov@xxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sm4250.dtsi | 46 ++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm4250.dtsi b/arch/arm64/boot/dts/qcom/sm4250.dtsi
index 1b9983ab122e..8873015c05b9 100644
--- a/arch/arm64/boot/dts/qcom/sm4250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm4250.dtsi
@@ -37,6 +37,16 @@ &cpu7 {
compatible = "qcom,kryo240";
};
+&swr0 {
+ pinctrl-0 = <&lpass_tx_swr_active>;
+ pinctrl-names = "default";
+};
+
+&swr1 {
+ pinctrl-0 = <&lpass_rx_swr_active>;
+ pinctrl-names = "default";
+};
+
&lpass_tlmm {
compatible = "qcom,sm4250-lpass-lpi-pinctrl";
gpio-ranges = <&lpass_tlmm 0 0 26>;
@@ -74,4 +84,40 @@ ext-mclk1-pins {
output-high;
};
};
+
+ lpass_tx_swr_active: lpass-tx-swr-active-state {
+ clk-pins {
+ pins = "gpio0";
+ function = "swr_tx_clk";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio1", "gpio2";
+ function = "swr_tx_data";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-bus-hold;
+ };
+ };
+
+ lpass_rx_swr_active: lpass-rx-swr-active-state {
+ clk-pins {
+ pins = "gpio3";
+ function = "swr_rx_clk";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio4", "gpio5";
+ function = "swr_rx_data";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-bus-hold;
+ };
+ };
};
--
2.45.2
