On Mon, Oct 21, 2024 at 10:21:57PM +0200, Gabor Juhos wrote:
> Since neither 'alpha' nor 'alpha_hi' is defined in the configuration,
> those will be initialized with zero values implicitly. By using zero
> alpha values, the output rate of the PLL will be the same whether
> alpha mode is enabled or not.
>
> Remove the superfluous initialization of the 'alpha_en_mask' member
> to make it clear that enabling alpha mode is not required to get the
> desired output rate.
>
> No functional changes, the initial rate of the PLL is the same both
> before and after the patch.
After going through DISPCC changes, I think the whole series is
incorrect: these PLL can change the rate (e.g. to facilitate CPU
frequency changes). Normally PLL ops do not check the alpha_en bit when
changing the rate, so the driver might try to set the PLL to the rate
which requires alpha value, while the alpha_en bit isn't set.
>
> Tested on TP-Link Archer AX55 v1 (IPQ5018).
>
> Signed-off-by: Gabor Juhos <j4g8y7@xxxxxxxxx>
> ---
> drivers/clk/qcom/apss-ipq-pll.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
> index e8632db2c542806e9527a22b54fe169e3e398a7a..dec2a5019cc77bf60142a86453883e336afc860f 100644
> --- a/drivers/clk/qcom/apss-ipq-pll.c
> +++ b/drivers/clk/qcom/apss-ipq-pll.c
> @@ -73,7 +73,6 @@ static const struct alpha_pll_config ipq5018_pll_config = {
> .main_output_mask = BIT(0),
> .aux_output_mask = BIT(1),
> .early_output_mask = BIT(3),
> - .alpha_en_mask = BIT(24),
> .status_val = 0x3,
> .status_mask = GENMASK(10, 8),
> .lock_det = BIT(2),
>
> --
> 2.47.0
>
--
With best wishes
Dmitry
