> Apologies for the delay in response. I understand that the PCS<->PHY > clocks may be out of the scope of PCS DT due to the reasons you mention. > However would like to clarify that the MII clocks referred to here, are > part of the connection between the MAC and PCS and not between PCS and PHY. > > Below is a diagram that shows the sub-blocks inside the 'UNIPHY' block > of IPQ9574 which houses the PCS and the serdes, along with the clock > connectivity. The MII Rx/Tx clocks are supplied from the NSS CC, to the > GMII channels between PCS and MAC. So, it seemed appropriate to have > these clocks described as part of the PCS DT node. > > +-------+ +---------+ +-------------------------+ > -----------|CMN PLL| | GCC | | NSSCC (Divider) | > |25/50mhz +----+--+ +----+----+ +--+-------+--------------+ > |clk | | ^ | > | 31.25M | SYS/AHB|clk RX/TX|clk +------------+ > | ref clk | | | | | > | | v | MII RX|TX clk MAC| RX/TX clk > | +--+---------+----------+-------+---+ +-+---------+ > | | | +----------------+ | | | | PPE | > v | | | UNIPHY0 V | | V | > +-------+ | v | +-----------+ (X)GMII| | | > | | | +---+---+ | |--------|------|-- MAC0 | > | | | | | | | (X)GMII| | | > | Quad | | |SerDes | | (X)PCS |--------|------|-- MAC1 | > | +<----+ | | | | (X)GMII| | | > |(X)GPHY| | | | | |--------|------|-- MAC2 | > | | | | | | | (X)GMII| | | > | | | +-------+ | |--------|------|-- MAC3 | > +-------+ | | | | | | > | +-----------+ | | | > +-----------------------------------+ | | Thanks for the detailed diagram. That always helps get things straight. Im i correct in says that MII RX|TX is identical to MAC RX|TX? These two clocks are used by the MAC and XPCS to clock data from one to the other? If they are the exact same clocks, i would suggest you use the same name, just to avoid confusion. Both XPCS and PPE are clock consumers, so both will have a phandle pointing to the NSSCC clock provider? > We had one other question on the approach used in the driver for PCS > clocks, could you please provide your comments. > > As we can see from the above diagram, each serdes in the UNIPHY block > provides the clocks to the NSSCC, and the PCS block consumes the MII > Rx/Tx clocks. In our current design, the PCS/UNIPHY driver registers a > provider driver for the clocks that the serdes supplies to the NSS CC. That sounds reasonable. > It also enables the MII Rx/Tx clocks which are supplied to the PCS from > the NSS CC. Would this be an acceptable design to have the PCS driver > register the clock provider driver and also consume the MII Rx/Tx > clocks? It may be worth noting that the serdes and PCS are part of the > same UNIPHY block and also share same register region. Does the SERDES consume the MII Rx/Tx? Your diagram indicates it does not. I'm just wondering if you have circular dependencies at runtime? Where you will need to be careful is probe time vs runtime. Since you have circular phandles you need to first create all the clock providers, and only then start the clock consumers. Otherwise you might get into an endless EPROBE_DEFER loop. Andrew
