On Tue, 03 Sep 2024 15:45:10 +0530, Rajendra Nayak wrote:
> On most modern qualcomm SoCs, the configuration necessary to enable the
> Tag/Data RAM related irqs being propagated to the SoC irq controller is
> already done in firmware (in DSF or 'DDR System Firmware')
>
> On some like the x1e80100, these registers aren't even accesible to the
> kernel causing a crash when edac device is probed.
>
> [...]
Applied, thanks!
[1/1] EDAC/qcom: Make irq configuration optional
commit: 0a97195d2181caced187acd7454464b8e37021d7
Best regards,
--
Bjorn Andersson <andersson@xxxxxxxxxx>
