On Mon, Sep 30, 2024 at 07:14:09PM +0530, Manivannan Sadhasivam wrote:
> Currently, if global IRQ is supported by the platform, only the Link up
> interrupt is enabled in the PARF_INT_ALL_MASK register. But on some Qcom
> platforms like SM8250, and X1E80100, MSIs are getting masked due to this.
> They require enabling the MSI interrupt bits in the register to unmask
> (enable) the MSIs.
"global IRQ" is a very generic name. If that's the official name, it
should at least be capitalized, e.g., "Global IRQ", to show that it is
a proper noun that refers to a specific IRQ.
> Even though the MSI interrupt enable bits in PARF_INT_ALL_MASK are
> described as 'diagnostic' interrupts in the internal documentation,
> disabling them masks MSI on these platforms. Due to this,
> MSIs were not
> reported to be received these platforms while supporting global IRQ.
I'm trying to parse "while supporting global IRQ." We basically
support global IRQ by installing qcom_pcie_global_irq_thread(), but of
course the device doesn't see that, so I assume it would be more
informative to say that MSIs are masked by some register setting.
The patch suggests that MSIs are masked internally unless
PARF_INT_MSI_DEV_0_7 is set in PARF_INT_ALL_MASK.
Are you saying that prior to 4581403f6792, MSIs did work? Does that
mean PARF_INT_MSI_DEV_0_7 was set by a bootloader or something, so
MSIs worked? And then 4581403f6792 came along and implicitly cleared
PARF_INT_MSI_DEV_0_7, so MSIs were then masked?
> So enable the MSI interrupts along with the Link up interrupt in the
> PARF_INT_ALL_MASK register if global IRQ is supported. This ensures that
> the MSIs continue to work and also the driver is able to catch the Link
> up interrupt for enumerating endpoint devices.
>
> Fixes: 4581403f6792 ("PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt")
> Reported-by: Konrad Dybcio <konradybcio@xxxxxxxxxx>
> Closes: https://lore.kernel.org/linux-pci/9a692c98-eb0a-4d86-b642-ea655981ff53@xxxxxxxxxx/
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index ef44a82be058..2b33d03ed054 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -133,6 +133,7 @@
>
> /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */
> #define PARF_INT_ALL_LINK_UP BIT(13)
> +#define PARF_INT_MSI_DEV_0_7 GENMASK(30, 23)
>
> /* PARF_NO_SNOOP_OVERIDE register fields */
> #define WR_NO_SNOOP_OVERIDE_EN BIT(1)
> @@ -1716,7 +1717,8 @@ static int qcom_pcie_probe(struct platform_device *pdev)
> goto err_host_deinit;
> }
>
> - writel_relaxed(PARF_INT_ALL_LINK_UP, pcie->parf + PARF_INT_ALL_MASK);
> + writel_relaxed(PARF_INT_ALL_LINK_UP | PARF_INT_MSI_DEV_0_7,
> + pcie->parf + PARF_INT_ALL_MASK);
> }
>
> qcom_pcie_icc_opp_update(pcie);
> --
> 2.25.1
>
