On 9/24/2024 10:31 PM, Johan Hovold wrote:
On Tue, Sep 24, 2024 at 03:14:42AM -0700, Qiang Yu wrote:
The pipediv2_clk's source from the same mux as pipe clock. So they have
same limitation, which is that the PHY sequence requires to enable these
local CBCs before the PHY is actually outputting a clock to them. This
means the clock won't actually turn on when we vote them. Hence, let's
skip the halt bit check of the pipediv2_clk, otherwise pipediv2_clk may
stuck at off state during bootup.
Suggested-by: Mike Tipton <quic_mdtipton@xxxxxxxxxxx>
Signed-off-by: Qiang Yu <quic_qianyu@xxxxxxxxxxx>
Reviewed-by: Konrad Dybcio <konradybcio@xxxxxxxxxx>
Looks like this one is missing a Fixes and CC stable tag. With that
added:
Will add Fixes and CC stable tag.
Thanks,
Qiang Yu
Reviewed-by: Johan Hovold <johan+linaro@xxxxxxxxxx>
Johan
