On Tue, Sep 24, 2024 at 04:42:02PM GMT, Mahadevan P wrote:
>
> On 9/12/2024 1:34 PM, Dmitry Baryshkov wrote:
> > On Thu, Sep 12, 2024 at 12:44:36PM GMT, Mahadevan wrote:
> > > Add definitions for the display hardware used on the
> > > Qualcomm SA8775P platform.
> > >
> > > Signed-off-by: Mahadevan <quic_mahap@xxxxxxxxxxx>
> > > ---
> > > .../msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 485 ++++++++++++++++++
> > > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +-
> > > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +-
> > > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +-
> > > 4 files changed, 491 insertions(+), 3 deletions(-)
> > > create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> > >
[...]
> > > +static const struct dpu_intf_cfg sa8775p_intf[] = {
> > > + {
> > > + .name = "intf_0", .id = INTF_0,
> > > + .base = 0x34000, .len = 0x280,
> > > + .features = INTF_SC7280_MASK,
> > > + .type = INTF_DP,
> > > + .controller_id = MSM_DP_CONTROLLER_0,
> > > + .prog_fetch_lines_worst_case = 24,
> > > + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> > > + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
> > > + }, {
> > > + .name = "intf_1", .id = INTF_1,
> > > + .base = 0x35000, .len = 0x300,
> > > + .features = INTF_SC7280_MASK,
> > > + .type = INTF_DSI,
> > > + .controller_id = MSM_DSI_CONTROLLER_0,
> > > + .prog_fetch_lines_worst_case = 24,
> > > + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> > > + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> > > + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
> > > + }, {
> > > + .name = "intf_2", .id = INTF_2,
> > > + .base = 0x36000, .len = 0x300,
> > > + .features = INTF_SC7280_MASK,
> > > + .type = INTF_DSI,
> > > + .controller_id = MSM_DSI_CONTROLLER_1,
> > > + .prog_fetch_lines_worst_case = 24,
> > > + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> > > + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> > > + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
> > > + }, {
> > > + .name = "intf_3", .id = INTF_3,
> > > + .base = 0x37000, .len = 0x280,
> > > + .features = INTF_SC7280_MASK,
> > > + .type = INTF_NONE,
> > > + .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
> > > + .prog_fetch_lines_worst_case = 24,
> > > + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> > > + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
> > > + }, {
> > > + .name = "intf_4", .id = INTF_4,
> > > + .base = 0x38000, .len = 0x280,
> > > + .features = INTF_SC7280_MASK,
> > > + .type = INTF_DP,
> > > + .controller_id = MSM_DP_CONTROLLER_1,
> > > + .prog_fetch_lines_worst_case = 24,
> > > + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
> > > + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
> > > + }, {
> > Where is intf_5 ?
>
>
> intf_5 of base address 0x39000 is not supported on this target.
Not supported by whom?
>
>
> >
> > > + .name = "intf_6", .id = INTF_6,
> > > + .base = 0x3A000, .len = 0x280,
> > > + .features = INTF_SC7280_MASK,
> > > + .type = INTF_NONE,
> > > + .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
> > > + .prog_fetch_lines_worst_case = 24,
> > > + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17),
> > > + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),
> > > + }, {
[skipped]
> > > @@ -1464,6 +1464,7 @@ static const struct of_device_id dpu_dt_match[] = {
> > > { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
> > > { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
> > > { .compatible = "qcom,sm8450-dpu", .data = &dpu_sm8450_cfg, },
> > > + { .compatible = "qcom,sa8775p-dpu", .data = &dpu_sa8775p_cfg, },
> > Wrong sorting order
>
>
> Sure will move below sm8650-dpu.
What makes you think that in a dictionary sa8775p comes after sm8650?
>
>
> >
> > > { .compatible = "qcom,sm8550-dpu", .data = &dpu_sm8550_cfg, },
> > > { .compatible = "qcom,sm8650-dpu", .data = &dpu_sm8650_cfg, },
> > > { .compatible = "qcom,x1e80100-dpu", .data = &dpu_x1e80100_cfg, },
> > > --
> > > 2.34.1
> > >
--
With best wishes
Dmitry
