On Fri, Sep 20, 2024 at 10:29:44AM -0700, Rob Clark wrote:
> On Fri, Sep 20, 2024 at 9:54 AM Akhil P Oommen <quic_akhilpo@xxxxxxxxxxx> wrote:
> >
> > On Tue, Sep 17, 2024 at 01:14:19PM +0200, Antonino Maniscalco wrote:
> > > Some userspace changes are necessary so add a flag for userspace to
> > > advertise support for preemption when creating the submitqueue.
> > >
> > > When this flag is not set preemption will not be allowed in the middle
> > > of the submitted IBs therefore mantaining compatibility with older
> > > userspace.
> > >
> > > The flag is rejected if preemption is not supported on the target, this
> > > allows userspace to know whether preemption is supported.
> >
> > Just curious, what is the motivation behind informing userspace about
> > preemption support?
>
> I think I requested that, as a "just in case" (because it would
> otherwise be awkward if we later needed to know the difference btwn
> drm/sched "preemption" which can only happen before submit is written
> to ring and "real" preemption)
Thanks. That makes sense.
-Akhil
>
> BR,
> -R
>
> > -Akhil
> >
> > >
> > > Signed-off-by: Antonino Maniscalco <antomani103@xxxxxxxxx>
> > > Tested-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx> # on SM8650-QRD
> > > ---
> > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 ++++++++----
> > > drivers/gpu/drm/msm/msm_submitqueue.c | 3 +++
> > > include/uapi/drm/msm_drm.h | 5 ++++-
> > > 3 files changed, 15 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > index 736f475d696f..edbcb6d229ba 100644
> > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > @@ -430,8 +430,10 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
> > > OUT_PKT7(ring, CP_SET_MARKER, 1);
> > > OUT_RING(ring, 0x101); /* IFPC disable */
> > >
> > > - OUT_PKT7(ring, CP_SET_MARKER, 1);
> > > - OUT_RING(ring, 0x00d); /* IB1LIST start */
> > > + if (submit->queue->flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT) {
> > > + OUT_PKT7(ring, CP_SET_MARKER, 1);
> > > + OUT_RING(ring, 0x00d); /* IB1LIST start */
> > > + }
> > >
> > > /* Submit the commands */
> > > for (i = 0; i < submit->nr_cmds; i++) {
> > > @@ -462,8 +464,10 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
> > > update_shadow_rptr(gpu, ring);
> > > }
> > >
> > > - OUT_PKT7(ring, CP_SET_MARKER, 1);
> > > - OUT_RING(ring, 0x00e); /* IB1LIST end */
> > > + if (submit->queue->flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT) {
> > > + OUT_PKT7(ring, CP_SET_MARKER, 1);
> > > + OUT_RING(ring, 0x00e); /* IB1LIST end */
> > > + }
> > >
> > > get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0),
> > > rbmemptr_stats(ring, index, cpcycles_end));
> > > diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/msm_submitqueue.c
> > > index 0e803125a325..9b3ffca3f3b4 100644
> > > --- a/drivers/gpu/drm/msm/msm_submitqueue.c
> > > +++ b/drivers/gpu/drm/msm/msm_submitqueue.c
> > > @@ -170,6 +170,9 @@ int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx,
> > > if (!priv->gpu)
> > > return -ENODEV;
> > >
> > > + if (flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT && priv->gpu->nr_rings == 1)
> > > + return -EINVAL;
> > > +
> > > ret = msm_gpu_convert_priority(priv->gpu, prio, &ring_nr, &sched_prio);
> > > if (ret)
> > > return ret;
> > > diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h
> > > index 3fca72f73861..f37858db34e6 100644
> > > --- a/include/uapi/drm/msm_drm.h
> > > +++ b/include/uapi/drm/msm_drm.h
> > > @@ -345,7 +345,10 @@ struct drm_msm_gem_madvise {
> > > * backwards compatibility as a "default" submitqueue
> > > */
> > >
> > > -#define MSM_SUBMITQUEUE_FLAGS (0)
> > > +#define MSM_SUBMITQUEUE_ALLOW_PREEMPT 0x00000001
> > > +#define MSM_SUBMITQUEUE_FLAGS ( \
> > > + MSM_SUBMITQUEUE_ALLOW_PREEMPT | \
> > > + 0)
> > >
> > > /*
> > > * The submitqueue priority should be between 0 and MSM_PARAM_PRIORITIES-1,
> > >
> > > --
> > > 2.46.0
> > >
