On 13.09.2024 9:51 PM, Rob Clark wrote: > From: Rob Clark <robdclark@xxxxxxxxxxxx> > > The CP_SMMU_TABLE_UPDATE _should_ be waiting for idle, but on some > devices (x1-85, possibly others), it seems to pass that barrier while > there are still things in the event completion FIFO waiting to be > written back to memory. Can we try to force-fault around here on other GPUs and perhaps limit this workaround? Akhil, do we have any insight on this? Konrad
