On Fri, Sep 13, 2024 at 01:37:21AM -0700, Qiang Yu wrote: > Add OPP table so that PCIe is able to adjust power domain performance > state and ICC peak bw according to PCIe gen speed and link width. > > Signed-off-by: Qiang Yu <quic_qianyu@xxxxxxxxxxx> > --- > Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 4 ++++ > 1 file changed, 4 insertions(+) Reviewed-by: Krzysztof Kozlowski <krzk@xxxxxxxxxx> Best regards, Krzysztof
