On Fri, Sep 13, 2024 at 01:37:22AM GMT, Qiang Yu wrote: > Currently driver supports only x4 lane based functionality using tx/rx and > tx2/rx2 pair of register sets. To support 8 lane functionality with PCIe3, > PCIe3 related QMP PHY provides additional programming which are available > as txz and rxz based register set. Hence adds txz and rxz based registers > usage and programming sequences. Phy register setting for txz and rxz will > be applied to all 8 lanes. Some lanes may have different settings on > several registers than txz/rxz, these registers should be programmed after > txz/rxz programming sequences completing. > > Besides, x1e80100 SoC uses QMP phy with version v6.30 for PCIe Gen4 x8. > Add the new register offsets in a dedicated header file. > > Signed-off-by: Qiang Yu <quic_qianyu@xxxxxxxxxxx> > --- > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 211 ++++++++++++++++++ > .../qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h | 25 +++ > drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h | 19 ++ > 3 files changed, 255 insertions(+) > create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h > create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> -- With best wishes Dmitry
