The PLLs on IPQ4019 cannot be reconfigured by design. The recommendation
is to program these PLLS only once. Since, the Bootloaders configure
the PLLs and clocks already. we did not support the recalc rate and
marked them as fixed clocks.
On 6/2/2016 3:48 AM, Stephen Boyd wrote:
This was a temporary solution until the PLL recalc code could be
written. When is the real clk driver coming so we can get rid of
these fixed rate clks being registered in this driver?
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