On Thu, Sep 05, 2024 at 10:48:13AM +0200, Johan Hovold wrote: > On Wed, Sep 04, 2024 at 02:50:57PM -0700, Doug Anderson wrote: > > How about this: we just change "uport->fifosize" to account for the 3 > > extra words? So it can be: > > > > ((port->tx_fifo_depth + 3) * port->tx_fifo_width) / BITS_PER_BYTE; > > > > ...then the cache will be correct and everything will work out. What > > do you think? > > I don't think uart_fifo_timeout traditionally accounts for the shift > register and we wait up to *twice* the time it takes to clear to fifo > anyway (in wait_until_sent). The intermediate register I found here > could perhaps be considered part of the fifo however. > > I'll give this some more thought. I decided to keep the fifo size as-is (e.g. as it is exported to user space) and only account for the shift and intermediate registers in the driver. I'm using the fifo size reported by the hardware to determine the timeout in v2. Johan
