On Tue, Sep 03, 2024 at 03:45:10PM GMT, Rajendra Nayak wrote:
> On most modern qualcomm SoCs, the configuration necessary to enable the
> Tag/Data RAM related irqs being propagated to the SoC irq controller is
> already done in firmware (in DSF or 'DDR System Firmware')
>
> On some like the x1e80100, these registers aren't even accesible to the
> kernel causing a crash when edac device is probed.
>
> Hence, make the irq configuration optional in the driver and mark x1e80100
> as the SoC on which this should be avoided.
>
> Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts")
> Reported-by: Bjorn Andersson <andersson@xxxxxxxxxx>
> Signed-off-by: Rajendra Nayak <quic_rjendra@xxxxxxxxxxx>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
Mani, would you like me to pick this through the qcom tree?
Regards,
Bjorn
> ---
> v2:
> Minor typo fixed in changelog
>
> drivers/edac/qcom_edac.c | 8 +++++---
> drivers/soc/qcom/llcc-qcom.c | 3 +++
> include/linux/soc/qcom/llcc-qcom.h | 2 ++
> 3 files changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
> index d3cd4cc54ace..96611ca09ac5 100644
> --- a/drivers/edac/qcom_edac.c
> +++ b/drivers/edac/qcom_edac.c
> @@ -342,9 +342,11 @@ static int qcom_llcc_edac_probe(struct platform_device *pdev)
> int ecc_irq;
> int rc;
>
> - rc = qcom_llcc_core_setup(llcc_driv_data, llcc_driv_data->bcast_regmap);
> - if (rc)
> - return rc;
> + if (!llcc_driv_data->ecc_irq_configured) {
> + rc = qcom_llcc_core_setup(llcc_driv_data, llcc_driv_data->bcast_regmap);
> + if (rc)
> + return rc;
> + }
>
> /* Allocate edac control info */
> edev_ctl = edac_device_alloc_ctl_info(0, "qcom-llcc", 1, "bank",
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index 8fa4ffd3a9b5..b1c0ae9991d6 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -139,6 +139,7 @@ struct qcom_llcc_config {
> int size;
> bool need_llcc_cfg;
> bool no_edac;
> + bool irq_configured;
> };
>
> struct qcom_sct_config {
> @@ -718,6 +719,7 @@ static const struct qcom_llcc_config x1e80100_cfg[] = {
> .need_llcc_cfg = true,
> .reg_offset = llcc_v2_1_reg_offset,
> .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
> + .irq_configured = true,
> },
> };
>
> @@ -1345,6 +1347,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
> drv_data->cfg = llcc_cfg;
> drv_data->cfg_size = sz;
> drv_data->edac_reg_offset = cfg->edac_reg_offset;
> + drv_data->ecc_irq_configured = cfg->irq_configured;
> mutex_init(&drv_data->lock);
> platform_set_drvdata(pdev, drv_data);
>
> diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
> index 9e9f528b1370..acad1f4cf854 100644
> --- a/include/linux/soc/qcom/llcc-qcom.h
> +++ b/include/linux/soc/qcom/llcc-qcom.h
> @@ -125,6 +125,7 @@ struct llcc_edac_reg_offset {
> * @num_banks: Number of llcc banks
> * @bitmap: Bit map to track the active slice ids
> * @ecc_irq: interrupt for llcc cache error detection and reporting
> + * @ecc_irq_configured: 'True' if firmware has already configured the irq propagation
> * @version: Indicates the LLCC version
> */
> struct llcc_drv_data {
> @@ -139,6 +140,7 @@ struct llcc_drv_data {
> u32 num_banks;
> unsigned long *bitmap;
> int ecc_irq;
> + bool ecc_irq_configured;
> u32 version;
> };
>
> --
> 2.34.1
>
