Hi Arnd, >> >>If you need the barrier after the write, it probably was already faulty >>before, because writel only implies a barrier before the store, not >>after. Of course all the barriers likely made the whole process so >>slow that you never hit that race in the end. > >ya, it could have worked in this way and i never saw a race issue before this. >The only reason for changing this was to optimise out the additonal barriers >that were happening. I do not see any issue now as well, only that the writes would >be faster. > I reposted a patch here [1] with comments, i had to delete the old accessors though as it became unused now. http://www.spinics.net/lists/arm-kernel/msg505448.html Regards, Sricharan -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
