On Thu, Aug 29, 2024 at 7:41 AM Krzysztof Kozlowski
<krzysztof.kozlowski@xxxxxxxxxx> wrote:
>
> DTS coding style expects labels to be lowercase. No functional impact.
> Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
> ---
> .../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 16 +--
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 158 ++++++++++-----------
> 2 files changed, 87 insertions(+), 87 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> index 6a28cab97189..83208b10f994 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> @@ -346,18 +346,18 @@ skin-temp-crit {
> cooling-maps {
> map0 {
> trip = <&skin_temp_alert0>;
> - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> };
>
> map1 {
> trip = <&skin_temp_alert1>;
> - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> };
> };
> };
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 80a57aa22839..2f2fb074d804 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -44,7 +44,7 @@ cpus {
> #address-cells = <2>;
> #size-cells = <0>;
>
> - CPU0: cpu@0 {
> + cpu0: cpu@0 {
> device_type = "cpu";
> compatible = "arm,cortex-a78c";
> reg = <0x0 0x0>;
> @@ -52,19 +52,19 @@ CPU0: cpu@0 {
> enable-method = "psci";
> capacity-dmips-mhz = <981>;
> dynamic-power-coefficient = <549>;
> - next-level-cache = <&L2_0>;
> - power-domains = <&CPU_PD0>;
> + next-level-cache = <&l2_0>;
> + power-domains = <&cpu_pd0>;
> power-domain-names = "psci";
> qcom,freq-domain = <&cpufreq_hw 0>;
> operating-points-v2 = <&cpu0_opp_table>;
> interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> - L2_0: l2-cache {
> + l2_0: l2-cache {
> compatible = "cache";
> cache-level = <2>;
> cache-unified;
> - next-level-cache = <&L3_0>;
> - L3_0: l3-cache {
> + next-level-cache = <&l3_0>;
> + l3_0: l3-cache {
> compatible = "cache";
> cache-level = <3>;
> cache-unified;
> @@ -72,7 +72,7 @@ L3_0: l3-cache {
> };
> };
>
> - CPU1: cpu@100 {
> + cpu1: cpu@100 {
> device_type = "cpu";
> compatible = "arm,cortex-a78c";
> reg = <0x0 0x100>;
> @@ -80,22 +80,22 @@ CPU1: cpu@100 {
> enable-method = "psci";
> capacity-dmips-mhz = <981>;
> dynamic-power-coefficient = <549>;
> - next-level-cache = <&L2_100>;
> - power-domains = <&CPU_PD1>;
> + next-level-cache = <&l2_100>;
> + power-domains = <&cpu_pd1>;
> power-domain-names = "psci";
> qcom,freq-domain = <&cpufreq_hw 0>;
> operating-points-v2 = <&cpu0_opp_table>;
> interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> - L2_100: l2-cache {
> + l2_100: l2-cache {
> compatible = "cache";
> cache-level = <2>;
> cache-unified;
> - next-level-cache = <&L3_0>;
> + next-level-cache = <&l3_0>;
> };
> };
>
> - CPU2: cpu@200 {
> + cpu2: cpu@200 {
> device_type = "cpu";
> compatible = "arm,cortex-a78c";
> reg = <0x0 0x200>;
> @@ -103,22 +103,22 @@ CPU2: cpu@200 {
> enable-method = "psci";
> capacity-dmips-mhz = <981>;
> dynamic-power-coefficient = <549>;
> - next-level-cache = <&L2_200>;
> - power-domains = <&CPU_PD2>;
> + next-level-cache = <&l2_200>;
> + power-domains = <&cpu_pd2>;
> power-domain-names = "psci";
> qcom,freq-domain = <&cpufreq_hw 0>;
> operating-points-v2 = <&cpu0_opp_table>;
> interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> - L2_200: l2-cache {
> + l2_200: l2-cache {
> compatible = "cache";
> cache-level = <2>;
> cache-unified;
> - next-level-cache = <&L3_0>;
> + next-level-cache = <&l3_0>;
> };
> };
>
> - CPU3: cpu@300 {
> + cpu3: cpu@300 {
> device_type = "cpu";
> compatible = "arm,cortex-a78c";
> reg = <0x0 0x300>;
> @@ -126,22 +126,22 @@ CPU3: cpu@300 {
> enable-method = "psci";
> capacity-dmips-mhz = <981>;
> dynamic-power-coefficient = <549>;
> - next-level-cache = <&L2_300>;
> - power-domains = <&CPU_PD3>;
> + next-level-cache = <&l2_300>;
> + power-domains = <&cpu_pd3>;
> power-domain-names = "psci";
> qcom,freq-domain = <&cpufreq_hw 0>;
> operating-points-v2 = <&cpu0_opp_table>;
> interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> - L2_300: l2-cache {
> + l2_300: l2-cache {
> compatible = "cache";
> cache-level = <2>;
> cache-unified;
> - next-level-cache = <&L3_0>;
> + next-level-cache = <&l3_0>;
> };
> };
>
> - CPU4: cpu@400 {
> + cpu4: cpu@400 {
> device_type = "cpu";
> compatible = "arm,cortex-x1c";
> reg = <0x0 0x400>;
> @@ -149,22 +149,22 @@ CPU4: cpu@400 {
> enable-method = "psci";
> capacity-dmips-mhz = <1024>;
> dynamic-power-coefficient = <590>;
> - next-level-cache = <&L2_400>;
> - power-domains = <&CPU_PD4>;
> + next-level-cache = <&l2_400>;
> + power-domains = <&cpu_pd4>;
> power-domain-names = "psci";
> qcom,freq-domain = <&cpufreq_hw 1>;
> operating-points-v2 = <&cpu4_opp_table>;
> interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> - L2_400: l2-cache {
> + l2_400: l2-cache {
> compatible = "cache";
> cache-level = <2>;
> cache-unified;
> - next-level-cache = <&L3_0>;
> + next-level-cache = <&l3_0>;
> };
> };
>
> - CPU5: cpu@500 {
> + cpu5: cpu@500 {
> device_type = "cpu";
> compatible = "arm,cortex-x1c";
> reg = <0x0 0x500>;
> @@ -172,22 +172,22 @@ CPU5: cpu@500 {
> enable-method = "psci";
> capacity-dmips-mhz = <1024>;
> dynamic-power-coefficient = <590>;
> - next-level-cache = <&L2_500>;
> - power-domains = <&CPU_PD5>;
> + next-level-cache = <&l2_500>;
> + power-domains = <&cpu_pd5>;
> power-domain-names = "psci";
> qcom,freq-domain = <&cpufreq_hw 1>;
> operating-points-v2 = <&cpu4_opp_table>;
> interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> - L2_500: l2-cache {
> + l2_500: l2-cache {
> compatible = "cache";
> cache-level = <2>;
> cache-unified;
> - next-level-cache = <&L3_0>;
> + next-level-cache = <&l3_0>;
> };
> };
>
> - CPU6: cpu@600 {
> + cpu6: cpu@600 {
> device_type = "cpu";
> compatible = "arm,cortex-x1c";
> reg = <0x0 0x600>;
> @@ -195,22 +195,22 @@ CPU6: cpu@600 {
> enable-method = "psci";
> capacity-dmips-mhz = <1024>;
> dynamic-power-coefficient = <590>;
> - next-level-cache = <&L2_600>;
> - power-domains = <&CPU_PD6>;
> + next-level-cache = <&l2_600>;
> + power-domains = <&cpu_pd6>;
> power-domain-names = "psci";
> qcom,freq-domain = <&cpufreq_hw 1>;
> operating-points-v2 = <&cpu4_opp_table>;
> interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> - L2_600: l2-cache {
> + l2_600: l2-cache {
> compatible = "cache";
> cache-level = <2>;
> cache-unified;
> - next-level-cache = <&L3_0>;
> + next-level-cache = <&l3_0>;
> };
> };
>
> - CPU7: cpu@700 {
> + cpu7: cpu@700 {
> device_type = "cpu";
> compatible = "arm,cortex-x1c";
> reg = <0x0 0x700>;
> @@ -218,53 +218,53 @@ CPU7: cpu@700 {
> enable-method = "psci";
> capacity-dmips-mhz = <1024>;
> dynamic-power-coefficient = <590>;
> - next-level-cache = <&L2_700>;
> - power-domains = <&CPU_PD7>;
> + next-level-cache = <&l2_700>;
> + power-domains = <&cpu_pd7>;
> power-domain-names = "psci";
> qcom,freq-domain = <&cpufreq_hw 1>;
> operating-points-v2 = <&cpu4_opp_table>;
> interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> - L2_700: l2-cache {
> + l2_700: l2-cache {
> compatible = "cache";
> cache-level = <2>;
> cache-unified;
> - next-level-cache = <&L3_0>;
> + next-level-cache = <&l3_0>;
> };
> };
>
> cpu-map {
> cluster0 {
> core0 {
> - cpu = <&CPU0>;
> + cpu = <&cpu0>;
> };
>
> core1 {
> - cpu = <&CPU1>;
> + cpu = <&cpu1>;
> };
>
> core2 {
> - cpu = <&CPU2>;
> + cpu = <&cpu2>;
> };
>
> core3 {
> - cpu = <&CPU3>;
> + cpu = <&cpu3>;
> };
>
> core4 {
> - cpu = <&CPU4>;
> + cpu = <&cpu4>;
> };
>
> core5 {
> - cpu = <&CPU5>;
> + cpu = <&cpu5>;
> };
>
> core6 {
> - cpu = <&CPU6>;
> + cpu = <&cpu6>;
> };
>
> core7 {
> - cpu = <&CPU7>;
> + cpu = <&cpu7>;
> };
> };
> };
> @@ -272,7 +272,7 @@ core7 {
> idle-states {
> entry-method = "psci";
>
> - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
> + little_cpu_sleep_0: cpu-sleep-0-0 {
> compatible = "arm,idle-state";
> idle-state-name = "little-rail-power-collapse";
> arm,psci-suspend-param = <0x40000004>;
> @@ -282,7 +282,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
> local-timer-stop;
> };
>
> - BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
> + big_cpu_sleep_0: cpu-sleep-1-0 {
> compatible = "arm,idle-state";
> idle-state-name = "big-rail-power-collapse";
> arm,psci-suspend-param = <0x40000004>;
> @@ -294,7 +294,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
> };
>
> domain-idle-states {
> - CLUSTER_SLEEP_0: cluster-sleep-0 {
> + cluster_sleep_0: cluster-sleep-0 {
> compatible = "domain-idle-state";
> arm,psci-suspend-param = <0x4100c344>;
> entry-latency-us = <3263>;
> @@ -593,57 +593,57 @@ psci {
> compatible = "arm,psci-1.0";
> method = "smc";
>
> - CPU_PD0: power-domain-cpu0 {
> + cpu_pd0: power-domain-cpu0 {
> #power-domain-cells = <0>;
> - power-domains = <&CLUSTER_PD>;
> - domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + power-domains = <&cluster_pd>;
> + domain-idle-states = <&little_cpu_sleep_0>;
> };
>
> - CPU_PD1: power-domain-cpu1 {
> + cpu_pd1: power-domain-cpu1 {
> #power-domain-cells = <0>;
> - power-domains = <&CLUSTER_PD>;
> - domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + power-domains = <&cluster_pd>;
> + domain-idle-states = <&little_cpu_sleep_0>;
> };
>
> - CPU_PD2: power-domain-cpu2 {
> + cpu_pd2: power-domain-cpu2 {
> #power-domain-cells = <0>;
> - power-domains = <&CLUSTER_PD>;
> - domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + power-domains = <&cluster_pd>;
> + domain-idle-states = <&little_cpu_sleep_0>;
> };
>
> - CPU_PD3: power-domain-cpu3 {
> + cpu_pd3: power-domain-cpu3 {
> #power-domain-cells = <0>;
> - power-domains = <&CLUSTER_PD>;
> - domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + power-domains = <&cluster_pd>;
> + domain-idle-states = <&little_cpu_sleep_0>;
> };
>
> - CPU_PD4: power-domain-cpu4 {
> + cpu_pd4: power-domain-cpu4 {
> #power-domain-cells = <0>;
> - power-domains = <&CLUSTER_PD>;
> - domain-idle-states = <&BIG_CPU_SLEEP_0>;
> + power-domains = <&cluster_pd>;
> + domain-idle-states = <&big_cpu_sleep_0>;
> };
>
> - CPU_PD5: power-domain-cpu5 {
> + cpu_pd5: power-domain-cpu5 {
> #power-domain-cells = <0>;
> - power-domains = <&CLUSTER_PD>;
> - domain-idle-states = <&BIG_CPU_SLEEP_0>;
> + power-domains = <&cluster_pd>;
> + domain-idle-states = <&big_cpu_sleep_0>;
> };
>
> - CPU_PD6: power-domain-cpu6 {
> + cpu_pd6: power-domain-cpu6 {
> #power-domain-cells = <0>;
> - power-domains = <&CLUSTER_PD>;
> - domain-idle-states = <&BIG_CPU_SLEEP_0>;
> + power-domains = <&cluster_pd>;
> + domain-idle-states = <&big_cpu_sleep_0>;
> };
>
> - CPU_PD7: power-domain-cpu7 {
> + cpu_pd7: power-domain-cpu7 {
> #power-domain-cells = <0>;
> - power-domains = <&CLUSTER_PD>;
> - domain-idle-states = <&BIG_CPU_SLEEP_0>;
> + power-domains = <&cluster_pd>;
> + domain-idle-states = <&big_cpu_sleep_0>;
> };
>
> - CLUSTER_PD: power-domain-cpu-cluster0 {
> + cluster_pd: power-domain-cpu-cluster0 {
> #power-domain-cells = <0>;
> - domain-idle-states = <&CLUSTER_SLEEP_0>;
> + domain-idle-states = <&cluster_sleep_0>;
> };
> };
>
> @@ -5111,7 +5111,7 @@ apps_rsc: rsc@18200000 {
> qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
> <WAKE_TCS 3>, <CONTROL_TCS 1>;
> label = "apps_rsc";
> - power-domains = <&CLUSTER_PD>;
> + power-domains = <&cluster_pd>;
>
> apps_bcm_voter: bcm-voter {
> compatible = "qcom,bcm-voter";
>
> --
> 2.43.0
>
>
Tested on the Thinkpad X13s
Tested-by: Steev Klimaszewski <steev@xxxxxxxx>
