On Thu, 01 Aug 2024 18:54:53 +0300, Abel Vesa wrote:
> Currently, only the RX and TX tables are written to the second PHY
> (port B) when the 4-lanes mode is configured, but according to Qualcomm
> internal documentation, the pcs, pcs_misc, serdes and ln_shrd tables need
> to be written as well.
>
>
Applied, thanks!
[1/1] phy: qcom: qmp-pcie: Configure all tables on port B PHY
commit: 00c5f32283f377ec60870bccbd518d9feb7fbc52
Best regards,
--
~Vinod
