DTS coding style expects labels to be lowercase. No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 162 +++++++++++++++++------------------
1 file changed, 81 insertions(+), 81 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 9dc0ee3eb98f..0a506ce4f43b 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -64,25 +64,25 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
- CPU0: cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a510";
reg = <0 0>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
- next-level-cache = <&L2_0>;
- power-domains = <&CPU_PD0>;
+ next-level-cache = <&l2_0>;
+ power-domains = <&cpu_pd0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
#cooling-cells = <2>;
- L2_0: l2-cache {
+ l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
- next-level-cache = <&L3_0>;
- L3_0: l3-cache {
+ next-level-cache = <&l3_0>;
+ l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
@@ -90,185 +90,185 @@ L3_0: l3-cache {
};
};
- CPU1: cpu@100 {
+ cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a510";
reg = <0 0x100>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
- next-level-cache = <&L2_100>;
- power-domains = <&CPU_PD1>;
+ next-level-cache = <&l2_100>;
+ power-domains = <&cpu_pd1>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
#cooling-cells = <2>;
- L2_100: l2-cache {
+ l2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
- next-level-cache = <&L3_0>;
+ next-level-cache = <&l3_0>;
};
};
- CPU2: cpu@200 {
+ cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a510";
reg = <0 0x200>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
- next-level-cache = <&L2_200>;
- power-domains = <&CPU_PD2>;
+ next-level-cache = <&l2_200>;
+ power-domains = <&cpu_pd2>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
#cooling-cells = <2>;
- L2_200: l2-cache {
+ l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
- next-level-cache = <&L3_0>;
+ next-level-cache = <&l3_0>;
};
};
- CPU3: cpu@300 {
+ cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a715";
reg = <0 0x300>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
- next-level-cache = <&L2_300>;
- power-domains = <&CPU_PD3>;
+ next-level-cache = <&l2_300>;
+ power-domains = <&cpu_pd3>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <270>;
#cooling-cells = <2>;
- L2_300: l2-cache {
+ l2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
- next-level-cache = <&L3_0>;
+ next-level-cache = <&l3_0>;
};
};
- CPU4: cpu@400 {
+ cpu4: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a715";
reg = <0 0x400>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
- next-level-cache = <&L2_400>;
- power-domains = <&CPU_PD4>;
+ next-level-cache = <&l2_400>;
+ power-domains = <&cpu_pd4>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <270>;
#cooling-cells = <2>;
- L2_400: l2-cache {
+ l2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
- next-level-cache = <&L3_0>;
+ next-level-cache = <&l3_0>;
};
};
- CPU5: cpu@500 {
+ cpu5: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a710";
reg = <0 0x500>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
- next-level-cache = <&L2_500>;
- power-domains = <&CPU_PD5>;
+ next-level-cache = <&l2_500>;
+ power-domains = <&cpu_pd5>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <270>;
#cooling-cells = <2>;
- L2_500: l2-cache {
+ l2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
- next-level-cache = <&L3_0>;
+ next-level-cache = <&l3_0>;
};
};
- CPU6: cpu@600 {
+ cpu6: cpu@600 {
device_type = "cpu";
compatible = "arm,cortex-a710";
reg = <0 0x600>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
- next-level-cache = <&L2_600>;
- power-domains = <&CPU_PD6>;
+ next-level-cache = <&l2_600>;
+ power-domains = <&cpu_pd6>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <270>;
#cooling-cells = <2>;
- L2_600: l2-cache {
+ l2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
- next-level-cache = <&L3_0>;
+ next-level-cache = <&l3_0>;
};
};
- CPU7: cpu@700 {
+ cpu7: cpu@700 {
device_type = "cpu";
compatible = "arm,cortex-x3";
reg = <0 0x700>;
clocks = <&cpufreq_hw 2>;
enable-method = "psci";
- next-level-cache = <&L2_700>;
- power-domains = <&CPU_PD7>;
+ next-level-cache = <&l2_700>;
+ power-domains = <&cpu_pd7>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 2>;
capacity-dmips-mhz = <1894>;
dynamic-power-coefficient = <588>;
#cooling-cells = <2>;
- L2_700: l2-cache {
+ l2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
- next-level-cache = <&L3_0>;
+ next-level-cache = <&l3_0>;
};
};
cpu-map {
cluster0 {
core0 {
- cpu = <&CPU0>;
+ cpu = <&cpu0>;
};
core1 {
- cpu = <&CPU1>;
+ cpu = <&cpu1>;
};
core2 {
- cpu = <&CPU2>;
+ cpu = <&cpu2>;
};
core3 {
- cpu = <&CPU3>;
+ cpu = <&cpu3>;
};
core4 {
- cpu = <&CPU4>;
+ cpu = <&cpu4>;
};
core5 {
- cpu = <&CPU5>;
+ cpu = <&cpu5>;
};
core6 {
- cpu = <&CPU6>;
+ cpu = <&cpu6>;
};
core7 {
- cpu = <&CPU7>;
+ cpu = <&cpu7>;
};
};
};
@@ -276,7 +276,7 @@ core7 {
idle-states {
entry-method = "psci";
- LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
+ little_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "silver-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@@ -286,7 +286,7 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
local-timer-stop;
};
- BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
+ big_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "gold-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@@ -296,7 +296,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
local-timer-stop;
};
- PRIME_CPU_SLEEP_0: cpu-sleep-2-0 {
+ prime_cpu_sleep_0: cpu-sleep-2-0 {
compatible = "arm,idle-state";
idle-state-name = "goldplus-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@@ -308,7 +308,7 @@ PRIME_CPU_SLEEP_0: cpu-sleep-2-0 {
};
domain-idle-states {
- CLUSTER_SLEEP_0: cluster-sleep-0 {
+ cluster_sleep_0: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000044>;
entry-latency-us = <750>;
@@ -316,7 +316,7 @@ CLUSTER_SLEEP_0: cluster-sleep-0 {
min-residency-us = <9144>;
};
- CLUSTER_SLEEP_1: cluster-sleep-1 {
+ cluster_sleep_1: cluster-sleep-1 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100c344>;
entry-latency-us = <2800>;
@@ -376,57 +376,57 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";
- CPU_PD0: power-domain-cpu0 {
+ cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_PD>;
- domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&little_cpu_sleep_0>;
};
- CPU_PD1: power-domain-cpu1 {
+ cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_PD>;
- domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&little_cpu_sleep_0>;
};
- CPU_PD2: power-domain-cpu2 {
+ cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_PD>;
- domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&little_cpu_sleep_0>;
};
- CPU_PD3: power-domain-cpu3 {
+ cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_PD>;
- domain-idle-states = <&BIG_CPU_SLEEP_0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&big_cpu_sleep_0>;
};
- CPU_PD4: power-domain-cpu4 {
+ cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_PD>;
- domain-idle-states = <&BIG_CPU_SLEEP_0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&big_cpu_sleep_0>;
};
- CPU_PD5: power-domain-cpu5 {
+ cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_PD>;
- domain-idle-states = <&BIG_CPU_SLEEP_0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&big_cpu_sleep_0>;
};
- CPU_PD6: power-domain-cpu6 {
+ cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_PD>;
- domain-idle-states = <&BIG_CPU_SLEEP_0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&big_cpu_sleep_0>;
};
- CPU_PD7: power-domain-cpu7 {
+ cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_PD>;
- domain-idle-states = <&PRIME_CPU_SLEEP_0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&prime_cpu_sleep_0>;
};
- CLUSTER_PD: power-domain-cluster {
+ cluster_pd: power-domain-cluster {
#power-domain-cells = <0>;
- domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
+ domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>;
};
};
@@ -4365,7 +4365,7 @@ apps_rsc: rsc@17a00000 {
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
<WAKE_TCS 2>, <CONTROL_TCS 0>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&cluster_pd>;
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";
--
2.43.0
