On Mon, Aug 26, 2024 at 11:36:28PM -0700, Qiang Yu wrote: > PCIe 3rd instance of X1E80100 support Gen 4x8 which needs different 8 lane > capable QMP PCIe PHY. Document Gen 4x8 PHY as separate module. > > Signed-off-by: Qiang Yu <quic_qianyu@xxxxxxxxxxx> > --- > .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 18 +++++++++++++++++- > 1 file changed, 17 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > index 03dbd02cf9e7..e122657490b1 100644 > --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > @@ -40,6 +40,7 @@ properties: > - qcom,sm8650-qmp-gen4x2-pcie-phy > - qcom,x1e80100-qmp-gen3x2-pcie-phy > - qcom,x1e80100-qmp-gen4x2-pcie-phy > + - qcom,x1e80100-qmp-gen4x8-pcie-phy > > reg: > minItems: 1 > @@ -47,7 +48,7 @@ properties: > > clocks: > minItems: 5 > - maxItems: 7 > + maxItems: 8 > > clock-names: > minItems: 5 > @@ -59,6 +60,7 @@ properties: > - const: pipe > - const: pipediv2 > - const: phy_aux > + - const: clkref_en That sounds like enabling clock ref, not the reference clock. > > power-domains: > maxItems: 1 > @@ -190,6 +192,19 @@ allOf: > clock-names: > minItems: 7 You need to now constrain other cases. Missing maxItems. Best regards, Krzysztof
