On Wed, Aug 21, 2024 at 10:08:41AM -0700, Shashank Babu Chinta Venkata wrote: > Add 16GT/s specific equalization and rx lane margining settings. These > settings are inline with respective PHY settings for 16GT/s > operation. > > In addition, current QCOM EP and RC drivers do not share common > codebase which would result in code duplication. Hence, adding > common files for code reusability among RC and EP drivers. > > v4 -> v5: > - Added additional parameter bandwidth to accommodate new icc path. > - Fixed typo. > - Picked up Reviewed-by tags. First, make sure to CC people that help reviewing your patches. Second, you don't mention that your previous series were completely broken as I pointed out here: https://lore.kernel.org/all/ZpDlf5xD035x2DqL@xxxxxxxxxxxxxxxxxxxx/ You apparently fixed that in v5 but conveniently forgot to mention it in the change log. Don't do that. Own your mistakes and learn from them. Third, don't send untested crap upstream. You clearly did not test your previous series properly and now v5 does not even build. Seriously, this is completely unacceptable and you're just wasting other people's time. > v3 -> v4: > - Addressed review comments from Mani and Konrad. > - Preceded subject line with pci: qcom: tags > > v2 -> v3: > - Replaced FIELD_GET/FIELD_PREP macros for bit operations. > - Renamed cmn to common. > - Avoided unnecessary argument validations. > - Addressed review comments from Konrad and Mani. > > v1 -> v2: > - Capitilized commit message to be inline with history > - Dropped stubs from header file. > - Moved Designware specific register offsets and masks to > pcie-designware.h header file. > - Applied settings based on bus data rate rather than link generation. > - Addressed review comments from Bjorn and Frank. Johan
