On Thu, Aug 22, 2024 at 12:18:23PM +0530, Manivannan Sadhasivam wrote: > On Wed, Aug 21, 2024 at 05:56:18PM -0500, Bjorn Helgaas wrote: > ... > > Although I do have the question of what happens if the RC deasserts > > PERST# before qcom-ep is loaded. We probably don't execute > > qcom_pcie_perst_deassert() in that case, so how does the init happen? > > PERST# is a level trigger signal. So even if the host has asserted > it before EP booted, the level will stay low and ep will detect it > while booting. The PERST# signal itself is definitely level oriented. I'm still skeptical about the *interrupt* from the PCIe controller being level-triggered, as I mentioned here: https://lore.kernel.org/r/20240815224735.GA57931@bhelgaas tegra194 is also dwc-based and has a similar PERST# interrupt but it's edge-triggered (tegra_pcie_ep_pex_rst_irq()), which I think is a cleaner implementation. Then you don't have to remember the current state, switch between high and low trigger, worry about races and missing a pulse, etc. > If it is an edge trigger signal, then ep wouldn't be able to catch > it as you suspected. Bjorn
