On Tue, Aug 20, 2024 at 10:02:42PM +0800, Luo Jie wrote: > The CMN PLL controller provides clocks to networking hardware blocks > on Qualcomm IPQ9574 SoC. It receives input clock from the on-chip Wi-Fi, > and produces output clocks at fixed rates. These output rates are > predetermined, and are unrelated to the input clock rate. The output > clocks are supplied to the Ethernet hardware such as PPE (packet > process engine) and the externally connected switch or PHY device. > > Signed-off-by: Luo Jie <quic_luoj@xxxxxxxxxxx> > --- > .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 70 ++++++++++++++++++++++ > include/dt-bindings/clock/qcom,ipq-cmn-pll.h | 15 +++++ > 2 files changed, 85 insertions(+) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
