PLEASE NOTE: b4 spazzed out, this is v2.
On 19/08/2024 14:59, Marc Gonzalez wrote:
> On qcom msm8998, writing to the last context bank of lpass_q6_smmu
> (base address 0x05100000) produces a system freeze & reboot.
>
> The hardware/hypervisor reports 13 context banks for the LPASS SMMU
> on msm8998, but only the first 12 are accessible...
> Override the number of context banks
>
> [ 2.546101] arm-smmu 5100000.iommu: probing hardware configuration...
> [ 2.552439] arm-smmu 5100000.iommu: SMMUv2 with:
> [ 2.558945] arm-smmu 5100000.iommu: stage 1 translation
> [ 2.563627] arm-smmu 5100000.iommu: address translation ops
> [ 2.568923] arm-smmu 5100000.iommu: non-coherent table walk
> [ 2.574566] arm-smmu 5100000.iommu: (IDR0.CTTW overridden by FW configuration)
> [ 2.580220] arm-smmu 5100000.iommu: stream matching with 12 register groups
> [ 2.587263] arm-smmu 5100000.iommu: 13 context banks (0 stage-2 only)
> [ 2.614447] arm-smmu 5100000.iommu: Supported page sizes: 0x63315000
> [ 2.621358] arm-smmu 5100000.iommu: Stage-1: 36-bit VA -> 36-bit IPA
> [ 2.627772] arm-smmu 5100000.iommu: preserved 0 boot mappings
>
> Specifically, here:
>
> qsmmu->bypass_cbndx = smmu->num_context_banks - 1;
> arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0);
>
> and here:
>
> arm_smmu_write_context_bank(smmu, i);
> arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT);
>
> It is likely that FW reserves the last context bank for its own use,
> thus a simple work-around would be: DON'T USE IT in Linux.
>
> For reference, the lpass_q6_smmu node looks like this:
>
> lpass_q6_smmu: iommu@5100000 {
> compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
> reg = <0x05100000 0x40000>;
> clocks = <&gcc HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
> clock-names = "iface";
>
> #global-interrupts = <0>;
> #iommu-cells = <1>;
> interrupts =
> <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
>
> power-domains = <&gcc LPASS_ADSP_GDSC>;
> status = "disabled";
> };
>
> Changes in v2:
> - Use the compatible prop instead of a specific prop to trigger work-around (Bjorn & Caleb)
> - Add qcom,msm8998-lpass-smmu compatible string
> - Link to v1: https://lore.kernel.org/r/20240814-smmu-v1-0-3d6c27027d5b@xxxxxxxxxx
>
> ---
> Marc Gonzalez (2):
> iommu/arm-smmu-qcom: hide last LPASS SMMU context bank from linux
> arm64: dts: qcom: msm8998: add qcom,msm8998-lpass-smmu compatible
>
> arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +-
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 5 +++++
> 2 files changed, 6 insertions(+), 1 deletion(-)
> ---
> base-commit: edb6307a8d9be5052ba5ce121e0bd55900ce44c4
> change-id: 20240814-smmu-d572c1a16aac
