On Tue, 06 Aug 2024 11:41:05 +0530, Amandeep Singh wrote:
> Update PLL offsets to DEFAULT_EVO to configure MDIO to 800MHz.
>
> The incorrect clock frequency leads to an incorrect MDIO clock. This,
> in turn, affects the MDIO hardware configurations as the divider is
> calculated from the MDIO clock frequency. If the clock frequency is
> not as expected, the MDIO register fails due to the generation of an
> incorrect MDIO frequency.
>
> [...]
Applied, thanks!
[1/1] clk: qcom: ipq9574: Update the alpha PLL type for GPLLs
commit: 6357efe3abead68048729adf11a9363881657939
Best regards,
--
Bjorn Andersson <andersson@xxxxxxxxxx>
