On qcom msm8998, writing to the last context bank of lpass_q6_smmu
(base address 0x05100000) produces a system freeze & reboot.
Specifically, here:
qsmmu->bypass_cbndx = smmu->num_context_banks - 1;
arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0);
and here:
arm_smmu_write_context_bank(smmu, i);
arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT);
It is likely that FW reserves the last context bank for its own use,
thus a simple work-around would be: DON'T USE IT in Linux.
This patch series:
1) introduces a DT prop "qcom,last-ctx-bank-reserved" to indicate
that FW reserves the last context bank of a given SMMU.
2) tweaks the driver to "hide" the last context bank from Linux.
For reference, the lpass_q6_smmu node looks like this:
lpass_q6_smmu: iommu@5100000 {
compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
reg = <0x05100000 0x40000>;
clocks = <&gcc HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
clock-names = "iface";
#global-interrupts = <0>;
#iommu-cells = <1>;
interrupts =
<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&gcc LPASS_ADSP_GDSC>;
status = "disabled";
};
---
Marc Gonzalez (2):
dt-bindings: arm-smmu: Add qcom,last-ctx-bank-reserved
iommu/arm-smmu-qcom: hide last context bank from linux
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 6 ++++++
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 5 +++++
2 files changed, 11 insertions(+)
---
base-commit: c934f6908ad1f210c1d1e289934d1182a6e7cb62
change-id: 20240814-smmu-d572c1a16aac
Best regards,
--
Marc Gonzalez <mgonzalez@xxxxxxxxxx>
