On Thu, Aug 01, 2024 at 06:54:53PM GMT, Abel Vesa wrote: > From: Qiang Yu <quic_qianyu@xxxxxxxxxxx> > > Currently, only the RX and TX tables are written to the second PHY > (port B) when the 4-lanes mode is configured, but according to Qualcomm > internal documentation, the pcs, pcs_misc, serdes and ln_shrd tables need > to be written as well. > > Signed-off-by: Qiang Yu <quic_qianyu@xxxxxxxxxxx> > Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx> > --- > Changes in v2: > - Reordered tables as Johan has suggested > - Link to v1: https://lore.kernel.org/r/20240726-phy-qcom-qmp-pcie-write-all-tbls-second-port-v1-1-751b9ee01184@xxxxxxxxxx > --- > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> -- With best wishes Dmitry
