On Sat, Jul 27, 2024 at 08:20:25PM GMT, Adam Skladowski wrote:
> From: Vladimir Lypak <vladimir.lypak@xxxxxxxxx>
>
> Add regs overrides for Cajon(PM8952) and Cajon v2(PM8953) codecs.
>
> Signed-off-by: Vladimir Lypak <vladimir.lypak@xxxxxxxxx>
> [Adam: Add Cajon support,add msg]
> Co-developed-by: Adam Skladowski <a39.skl@xxxxxxxxx>
> Signed-off-by: Adam Skladowski <a39.skl@xxxxxxxxx>
> ---
> sound/soc/codecs/msm8916-wcd-analog.c | 63 +++++++++++++++++++++++++--
> 1 file changed, 60 insertions(+), 3 deletions(-)
>
> diff --git a/sound/soc/codecs/msm8916-wcd-analog.c b/sound/soc/codecs/msm8916-wcd-analog.c
> index 9ca381812975..daf65f5d4e99 100644
> --- a/sound/soc/codecs/msm8916-wcd-analog.c
> +++ b/sound/soc/codecs/msm8916-wcd-analog.c
> @@ -250,6 +250,7 @@
> SPKR_DRV_CAL_EN | SPKR_DRV_SETTLE_EN | \
> SPKR_DRV_FW_EN | SPKR_DRV_BOOST_SET | \
> SPKR_DRV_CMFB_SET | SPKR_DRV_GAIN_SET)
> +#define CDC_A_SPKR_ANA_BIAS_SET (0xf1B3)
> #define CDC_A_SPKR_OCP_CTL (0xf1B4)
> #define CDC_A_SPKR_PWRSTG_CTL (0xf1B5)
> #define SPKR_PWRSTG_CTL_DAC_EN_MASK BIT(0)
> @@ -264,12 +265,15 @@
>
> #define CDC_A_SPKR_DRV_DBG (0xf1B7)
> #define CDC_A_CURRENT_LIMIT (0xf1C0)
> +#define CDC_A_BYPASS_MODE (0xf1C2)
> #define CDC_A_BOOST_EN_CTL (0xf1C3)
> #define CDC_A_SLOPE_COMP_IP_ZERO (0xf1C4)
> #define CDC_A_SEC_ACCESS (0xf1D0)
> #define CDC_A_PERPH_RESET_CTL3 (0xf1DA)
> #define CDC_A_PERPH_RESET_CTL4 (0xf1DB)
>
> +#define CDC_A_RX_EAR_STATUS (0xf1A1)
This one should go before CDC_A_SPKR_DAC_CTL
> +
> #define MSM8916_WCD_ANALOG_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
> SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
> #define MSM8916_WCD_ANALOG_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
> @@ -715,6 +719,50 @@ static const struct reg_default wcd_reg_defaults_2_0[] = {
> {CDC_A_MASTER_BIAS_CTL, 0x30},
> };
>
> +static const struct reg_default wcd_reg_defaults_cajon[] = {
> + {CDC_A_RX_COM_OCP_CTL, 0xD1},
> + {CDC_A_RX_COM_OCP_COUNT, 0xFF},
> + {CDC_D_SEC_ACCESS, 0xA5},
> + {CDC_D_PERPH_RESET_CTL3, 0x0F},
> + {CDC_A_TX_1_2_OPAMP_BIAS, 0x4C},
> + {CDC_A_NCP_FBCTRL, 0xA8},
> + {CDC_A_NCP_VCTRL, 0xA4},
> + {CDC_A_SPKR_DRV_CTL, 0x69},
> + {CDC_A_SPKR_DRV_DBG, 0x01},
> + {CDC_A_SEC_ACCESS, 0xA5},
> + {CDC_A_PERPH_RESET_CTL3, 0x0F},
> + {CDC_A_CURRENT_LIMIT, 0x82},
> + {CDC_A_SPKR_ANA_BIAS_SET, 0x41},
> + {CDC_A_SPKR_DAC_CTL, 0x03},
> + {CDC_A_SPKR_OCP_CTL, 0xE1},
> + {CDC_A_RX_HPH_BIAS_PA, 0xFA},
> + {CDC_A_MASTER_BIAS_CTL, 0x30},
> + {CDC_A_MICB_1_INT_RBIAS, 0x00},
> +};
> +
> +static const struct reg_default wcd_reg_defaults_cajon_2_0[] = {
> + {CDC_A_RX_COM_OCP_CTL, 0xD1},
> + {CDC_A_RX_COM_OCP_COUNT, 0xFF},
> + {CDC_D_SEC_ACCESS, 0xA5},
> + {CDC_D_PERPH_RESET_CTL3, 0x0F},
> + {CDC_A_TX_1_2_OPAMP_BIAS, 0x4C},
> + {CDC_A_NCP_FBCTRL, 0xA8},
> + {CDC_A_NCP_VCTRL, 0xA4},
> + {CDC_A_SPKR_DRV_CTL, 0x69},
> + {CDC_A_SPKR_DRV_DBG, 0x01},
> + {CDC_A_SEC_ACCESS, 0xA5},
> + {CDC_A_PERPH_RESET_CTL3, 0x0F},
> + {CDC_A_CURRENT_LIMIT, 0xA2},
> + {CDC_A_BYPASS_MODE, 0x18},
> + {CDC_A_SPKR_ANA_BIAS_SET, 0x41},
> + {CDC_A_SPKR_DAC_CTL, 0x03},
> + {CDC_A_SPKR_OCP_CTL, 0xE1},
> + {CDC_A_RX_HPH_BIAS_PA, 0xFA},
> + {CDC_A_RX_EAR_STATUS, 0x10},
> + {CDC_A_MASTER_BIAS_CTL, 0x30},
> + {CDC_A_MICB_1_INT_RBIAS, 0x00},
> +};
> +
> static int pm8916_wcd_analog_probe(struct snd_soc_component *component)
> {
> struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev);
> @@ -738,9 +786,18 @@ static int pm8916_wcd_analog_probe(struct snd_soc_component *component)
> snd_soc_component_write(component, CDC_D_PERPH_RESET_CTL4, 0x01);
> snd_soc_component_write(component, CDC_A_PERPH_RESET_CTL4, 0x01);
>
> - for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++)
> - snd_soc_component_write(component, wcd_reg_defaults_2_0[reg].reg,
> - wcd_reg_defaults_2_0[reg].def);
> + if (priv->codec_version == 4)
> + for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_cajon_2_0); reg++)
> + snd_soc_component_write(component, wcd_reg_defaults_cajon_2_0[reg].reg,
> + wcd_reg_defaults_cajon_2_0[reg].def);
> + else if (priv->codec_version == 3)
> + for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_cajon); reg++)
> + snd_soc_component_write(component, wcd_reg_defaults_cajon[reg].reg,
> + wcd_reg_defaults_cajon[reg].def);
> + else
> + for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++)
> + snd_soc_component_write(component, wcd_reg_defaults_2_0[reg].reg,
> + wcd_reg_defaults_2_0[reg].def);
I have mixed feelings towards this. Would it be better to use
PMIC-specific compatibles and pass register init as match data instead?
>
> priv->component = component;
>
> --
> 2.45.2
>
--
With best wishes
Dmitry
