On Fri, Jul 19, 2024 at 07:32:23PM -0400, Frank Li wrote:
> On Wed, Jul 17, 2024 at 10:33:17PM +0530, Manivannan Sadhasivam via B4 Relay wrote:
> > From: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> >
> > Historically, Qcom PCIe RC controllers lack standard hotplug support. So
> > when an endpoint is attached to the SoC, users have to rescan the bus
> > manually to enumerate the device. But this can be avoided by simulating the
> > PCIe hotplug using Qcom specific way.
> >
> > Qcom PCIe RC controllers are capable of generating the 'global' SPI
> > interrupt to the host CPUs. The device driver can use this event to
> > identify events such as PCIe link specific events, safety events etc...
> >
> > One such event is the PCIe Link up event generated when an endpoint is
> > detected on the bus and the Link is 'up'. This event can be used to
> > simulate the PCIe hotplug in the Qcom SoCs.
>
> Does hardware auto send out training pattern when EP boot after RC scan pci
> bus? Who trigger start link trainning?
>
This is taken care by the DWC driver. It starts link training during
dw_pcie_host_init().
- Mani
> Frank
>
> >
> > So add support for capturing the PCIe Link up event using the 'global'
> > interrupt in the driver. Once the Link up event is received, the bus
> > underneath the host bridge is scanned to enumerate PCIe endpoint devices,
> > thus simulating hotplug.
> >
> > All of the Qcom SoCs have only one rootport per controller instance. So
> > only a single 'Link up' event is generated for the PCIe controller.
> >
> > Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> > ---
> > drivers/pci/controller/dwc/pcie-qcom.c | 55 +++++++++++++++++++++++++++++++++-
> > 1 file changed, 54 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> > index 0180edf3310e..a1d678fe7fa5 100644
> > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > @@ -50,6 +50,9 @@
> > #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8
> > #define PARF_Q2A_FLUSH 0x1ac
> > #define PARF_LTSSM 0x1b0
> > +#define PARF_INT_ALL_STATUS 0x224
> > +#define PARF_INT_ALL_CLEAR 0x228
> > +#define PARF_INT_ALL_MASK 0x22c
> > #define PARF_SID_OFFSET 0x234
> > #define PARF_BDF_TRANSLATE_CFG 0x24c
> > #define PARF_SLV_ADDR_SPACE_SIZE 0x358
> > @@ -121,6 +124,9 @@
> > /* PARF_LTSSM register fields */
> > #define LTSSM_EN BIT(8)
> >
> > +/* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */
> > +#define PARF_INT_ALL_LINK_UP BIT(13)
> > +
> > /* PARF_NO_SNOOP_OVERIDE register fields */
> > #define WR_NO_SNOOP_OVERIDE_EN BIT(1)
> > #define RD_NO_SNOOP_OVERIDE_EN BIT(3)
> > @@ -1488,6 +1494,29 @@ static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie)
> > qcom_pcie_link_transition_count);
> > }
> >
> > +static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data)
> > +{
> > + struct qcom_pcie *pcie = data;
> > + struct dw_pcie_rp *pp = &pcie->pci->pp;
> > + struct device *dev = pcie->pci->dev;
> > + u32 status = readl_relaxed(pcie->parf + PARF_INT_ALL_STATUS);
> > +
> > + writel_relaxed(status, pcie->parf + PARF_INT_ALL_CLEAR);
> > +
> > + if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) {
> > + dev_dbg(dev, "Received Link up event. Starting enumeration!\n");
> > + /* Rescan the bus to enumerate endpoint devices */
> > + pci_lock_rescan_remove();
> > + pci_rescan_bus(pp->bridge->bus);
> > + pci_unlock_rescan_remove();
> > + } else {
> > + dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n",
> > + status);
> > + }
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > static int qcom_pcie_probe(struct platform_device *pdev)
> > {
> > const struct qcom_pcie_cfg *pcie_cfg;
> > @@ -1498,7 +1527,8 @@ static int qcom_pcie_probe(struct platform_device *pdev)
> > struct dw_pcie_rp *pp;
> > struct resource *res;
> > struct dw_pcie *pci;
> > - int ret;
> > + int ret, irq;
> > + char *name;
> >
> > pcie_cfg = of_device_get_match_data(dev);
> > if (!pcie_cfg || !pcie_cfg->ops) {
> > @@ -1617,6 +1647,27 @@ static int qcom_pcie_probe(struct platform_device *pdev)
> > goto err_phy_exit;
> > }
> >
> > + name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_global_irq%d",
> > + pci_domain_nr(pp->bridge->bus));
> > + if (!name) {
> > + ret = -ENOMEM;
> > + goto err_host_deinit;
> > + }
> > +
> > + irq = platform_get_irq_byname_optional(pdev, "global");
> > + if (irq > 0) {
> > + ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
> > + qcom_pcie_global_irq_thread,
> > + IRQF_ONESHOT, name, pcie);
> > + if (ret) {
> > + dev_err_probe(&pdev->dev, ret,
> > + "Failed to request Global IRQ\n");
> > + goto err_host_deinit;
> > + }
> > +
> > + writel_relaxed(PARF_INT_ALL_LINK_UP, pcie->parf + PARF_INT_ALL_MASK);
> > + }
> > +
> > qcom_pcie_icc_opp_update(pcie);
> >
> > if (pcie->mhi)
> > @@ -1624,6 +1675,8 @@ static int qcom_pcie_probe(struct platform_device *pdev)
> >
> > return 0;
> >
> > +err_host_deinit:
> > + dw_pcie_host_deinit(pp);
> > err_phy_exit:
> > phy_exit(pcie->phy);
> > err_pm_runtime_put:
> >
> > --
> > 2.25.1
> >
> >
--
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