Since 1788cf6a91d9 "tty: serial: switch from circ_buf to kfifo" serial
transmit when using DMA uses kfifo with a SG list with a single entry.
This obviously lead to 2 separate DMA transfers when the buffer wraps
around.
On the receiving end depending on the UART the receive DMA might
terminate when there is a moment of silence (an interchar gap) of a few
(typcially 5) characters length. The receivers FIFO will help to extend
that time (depending on FIFO length and threshold). Currently high
speed UARTs (HSU) can have baud rates of 3.5MBd which means terminating
a DMA transfer and handling a receive interrupt to set up a new DMA
transfer has to complete in 180us which is hard to guarantee. Especially
under heavy interrupt load.
As most serial protocols will transfer maximally a buffer length at a
time it makes sense to eliminate the interchar gap on buffer wraps by
using a SG list with 2 entries.
The following patch has been tested on Merrifield (Intel Edison) which
is slow (500MHz) but has a HSU that can transmit up to 3.5MBd.
This patch should be viewed as a preparation for a follow-up patch that
remove the interrupt on the receiving end entirely.
But first I would like to make sure that: 1) either all users can
actually handle 2 SG entries 2) if not, get your advice on how to best
make the number of entries configurable per platform
Possibly on RZN1 due to aa63d786cea2 ("serial: 8250: dw: Add support for
DMA flow controlling devices") we might anticipate problems.
Please test on your platform and let me know your suggestions.
Thanks!
Ferry Toth (1):
tty: serial: 8250_dma: use sgl with 2 nents to take care of buffer
wrap
drivers/tty/serial/8250/8250_dma.c | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
--
2.43.0
