While trying to fix a crash when display is started late in the boot process, I ran on multiple issues with the DISPCC clock definitions that needed some fixups. Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx> --- Changes in v2: - Squashed patch 2 into patch 1 - Dropped shared_ops to disp_cc_sleep_clk_src & disp_cc_xo_clk_src as Taniya recommends - Dropped patch 3 - Removed wait_val fields updates from GDSC, this requires a larger solution - Link to v1: https://lore.kernel.org/r/20240621-topic-sm8650-upstream-fix-dispcc-v1-0-7b297dd9fcc1@xxxxxxxxxx --- Neil Armstrong (3): clk: qcom: dispcc-sm8650: Park RCG's clk source at XO during disable clk: qcom: dispcc-sm8650: add missing CLK_SET_RATE_PARENT flag clk: qcom: dispcc-sm8650: Update the GDSC flags drivers/clk/qcom/dispcc-sm8650.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) --- base-commit: b992b79ca8bc336fa8e2c80990b5af80ed8f36fd change-id: 20240621-topic-sm8650-upstream-fix-dispcc-a1994038c003 Best regards, -- Neil Armstrong <neil.armstrong@xxxxxxxxxx>
