On Wed, 05 Jun 2024 20:45:37 +0800, Luo Jie wrote:
> qca8xxx is 4 * 2.5GBaseT ports chip, working as switch mode
> named by qca8386, or working as PHY mode named by qca8084,
> clock hardware reigster is accessed by MDIO bus.
>
> This patch series add the clock controller of qca8363/qca8084,
> and add the clock ops clk_branch2_prepare_ops to avoid spin lock
> used during the clock operation of qca8k clock controller where
> the sleep happens when accessing clock control register by MDIO
> bus.
>
> [...]
Applied, thanks!
[1/4] clk: qcom: branch: Add clk_branch2_prepare_ops
commit: 7311bbfff31c4961c57d94c165fa843f155f8236
[2/4] dt-bindings: clock: add qca8386/qca8084 clock and reset definitions
commit: 80bbd1c355d661678d2a25bd36e739b6925e7a4e
[3/4] clk: qcom: common: commonize qcom_cc_really_probe
commit: 9f93a0a428606341da25bf2a00244701b58e08b9
[4/4] clk: qcom: add clock controller driver for qca8386/qca8084
commit: 2441b965c4c7adae0b4a7825f7acb67d44c3cd38
Best regards,
--
Bjorn Andersson <andersson@xxxxxxxxxx>
